3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

Further exploitation of the spatial domain, as in Massive MIMO (MaMi) systems, is imperative to meet future communication requirements [1]. Up-scaling of conventional 4×4 small-scale MIMO implementations to MaMi is prohibitive in-terms of flexibility, as well as area and power cost. This work discloses a 1.1mm2 128×8 MaMi baseband chip, achieving up to 12dB array and 2× spatial multiplexing gains. The area cost compared to previous state-of-the-art MIMO implementations [2-3], is reduced by 53% and 17% for up- and down-link, respectively. Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.

Details

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Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Communication Systems
Original languageEnglish
Title of host publication2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages60-61
Number of pages2
Volume60
ISBN (Electronic)9781509037575
StatePublished - 2017 Mar 2
Peer-reviewedYes
Event64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States

Conference

Conference64th IEEE International Solid-State Circuits Conference, ISSCC 2017
CountryUnited States
CitySan Francisco
Period2017/02/052017/02/09