Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

Test scheduling and Test Access Mechanism (TAM)design are two important tasks in the development of a System-on-Chip (SOC)test solution.Previous test scheduling techniques assume a dedicated designed TAM which have the advantage of high exibility in the scheduling process. However,hardware verhead for implementing the TAM and additional routing is required of the TAMs.In this paper we propose a technique that makes use of the existing functional buses for the test data transportation inside the SOC.We have dealt with the test scheduling problem with this new assumption and developed a technique to minimize the test-controller and buffer size for a bus- based multi-core SOC.We have solved the problem by using a constraint logic pr gramming (CLP) technique and demonstrated the ef ciency of our approach by running experiments on benchmark designs.

Details

Authors
External organisations
  • External Organization - Unknown
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • test access mechanisms, TAM, system-on-chip, SOC, data transportation, constraint logic programming, test scheduling
Original languageEnglish
Title of host publication[Host publication title missing]
PublisherIEEE--Institute of Electrical and Electronics Engineers Inc.
Pages385-392
ISBN (Print)0-7695-2042-1
StatePublished - 2003
Peer-reviewedYes
Externally publishedYes
Event18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03 - Boston, MA, United States
Duration: 2003 Nov 32003 Nov 5

Publication series

Name
ISSN (Print)1550-5774

Conference

Conference18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03
CountryUnited States
CityBoston, MA
Period2003/11/032003/11/05