Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

Research output: Contribution to journalLetter

Abstract

Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.

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Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • vertical, nanowire, InAs, MOSFET, transistor, gate-last, self-aligned
Original languageEnglish
Pages (from-to) 966 - 969
Number of pages4
JournalIEEE Electron Device Letters
Volume37
Issue number8
StatePublished - 2016 Aug 8
Peer-reviewedYes