Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

Research output: Contribution to journalLetter

Bibtex

@article{5a9dc9e423e3426b8bee85e40faa56e4,
title = "Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si",
abstract = "Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.",
keywords = "vertical, nanowire, InAs, MOSFET, transistor, gate-last, self-aligned",
author = "Martin Berg and Olli-Pekka Kilpi and Karl-Magnus Persson and Johannes Svensson and Markus Hellenbrand and Erik Lind and Lars-Erik Wernersson",
year = "2016",
month = "8",
doi = "10.1109/LED.2016.2581918",
volume = "37",
pages = "966 -- 969",
journal = "IEEE Electron Device Letters",
issn = "0741-3106",
publisher = "IEEE--Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}