III/V Nanowire FETs for CMOS?

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

III/V MOS transistors are currently attracting considerable attention. The main driving force is that the advantageous transport properties in III/V materials are expected to increase the drive current in the MOS transistors. Major challenges for the III/V MOS technologies include the growth of high-quality III/V materials oil Si Substrates and the control of the MOS interface. Using the nanowire technology, we have recently demonstrated enhancement mode operation of 50 nm L-g InAs nanowire wrap-gate transistors in a vertical configuration. They demonstrate a transconductance of 0.5 S/mm, an inverse sub-threshold slope of about 80 mV/dec., and an I-on/I-off ratio > 1000 for a drive voltage of V-d=0.5 V. These results show promise for the use of nanowires in CMOS applications.

Details

Authors
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Condensed Matter Physics
  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publicationSige, Ge, And Related Compounds 3: Materials, Processing, And Devices
PublisherElectrochemical Society
Pages741-743
Volume16
StatePublished - 2008
Peer-reviewedYes
Event3rd International SiGe, Ge, and Related Compounds Symposium - Honolulu, HI, United States

Publication series

Name
Number10
Volume16
ISSN (Print)1938-6737
ISSN (Electronic)1938-5862

Conference

Conference3rd International SiGe, Ge, and Related Compounds Symposium
CountryUnited States
CityHonolulu, HI
Period2008/10/122008/10/17