InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Standard

InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v. / Zota, Cezar B.; Lindelöw, Fredrik; Wernersson, Lars Erik; Lind, Erik.

2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7573418.

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Harvard

Zota, CB, Lindelöw, F, Wernersson, LE & Lind, E 2016, InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v. in 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016., 7573418, Institute of Electrical and Electronics Engineers Inc., 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016, Honolulu, United States, 2016/06/13. DOI: 10.1109/VLSIT.2016.7573418

APA

Zota, C. B., Lindelöw, F., Wernersson, L. E., & Lind, E. (2016). InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v. In 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016 [7573418] Institute of Electrical and Electronics Engineers Inc.. DOI: 10.1109/VLSIT.2016.7573418

CBE

Zota CB, Lindelöw F, Wernersson LE, Lind E. 2016. InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v. In 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Institute of Electrical and Electronics Engineers Inc. Available from: 10.1109/VLSIT.2016.7573418

MLA

Zota, Cezar B. et al. "InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v". 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Institute of Electrical and Electronics Engineers Inc.2016. Available: 10.1109/VLSIT.2016.7573418

Vancouver

Zota CB, Lindelöw F, Wernersson LE, Lind E. InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v. In 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Institute of Electrical and Electronics Engineers Inc.2016. 7573418. Available from, DOI: 10.1109/VLSIT.2016.7573418

Author

Zota, Cezar B. ; Lindelöw, Fredrik ; Wernersson, Lars Erik ; Lind, Erik. / InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v. 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Institute of Electrical and Electronics Engineers Inc., 2016.

RIS

TY - CHAP

T1 - InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v

AU - Zota,Cezar B.

AU - Lindelöw,Fredrik

AU - Wernersson,Lars Erik

AU - Lind,Erik

PY - 2016/9/21

Y1 - 2016/9/21

N2 - We report on In0.85Ga0.15As nanowire MOSFETs (NWFETs) with record performance in several key VLSI metrics. These devices exhibit ION = 555 μA/μm (at IOFF = 100 nA/μm and VDD = 0.5 V), ION = 365 μA/μm (at IOFF = 10 nA/μm and VDD = 0.5 V) and a quality factor Q = gm/SS of 40, all of which are the highest reported for a III-V as well as silicon transistor. Furthermore, a highly scalable, self-Aligned gate-last fabrication process is utilized, with a single nanowire as the channel. The devices use a 45° angle between the nanowire and the contacts, which allows for up to a 1.4 times longer gate length at a given pitch.

AB - We report on In0.85Ga0.15As nanowire MOSFETs (NWFETs) with record performance in several key VLSI metrics. These devices exhibit ION = 555 μA/μm (at IOFF = 100 nA/μm and VDD = 0.5 V), ION = 365 μA/μm (at IOFF = 10 nA/μm and VDD = 0.5 V) and a quality factor Q = gm/SS of 40, all of which are the highest reported for a III-V as well as silicon transistor. Furthermore, a highly scalable, self-Aligned gate-last fabrication process is utilized, with a single nanowire as the channel. The devices use a 45° angle between the nanowire and the contacts, which allows for up to a 1.4 times longer gate length at a given pitch.

UR - http://www.scopus.com/inward/record.url?scp=84990943483&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2016.7573418

DO - 10.1109/VLSIT.2016.7573418

M3 - Paper in conference proceeding

BT - 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016

PB - Institute of Electrical and Electronics Engineers Inc.

ER -