Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.

Details

Authors
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting, IEDM
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2016-February
ISBN (Print)9781467398930
StatePublished - 2016 Feb 16
Peer-reviewedYes
Event61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States

Conference

Conference61st IEEE International Electron Devices Meeting, IEDM 2015
CountryUnited States
CityWashington
Period2015/12/072015/12/09