Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Bibtex

@inproceedings{ef8834bb39fb4a5090f298797f0ba7a8,
title = "Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si",
abstract = "In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.",
author = "Martin Berg and Karl-Magnus Persson and Olli-Pekka Kilpi and Johannes Svensson and Erik Lind and Lars-Erik Wernersson",
year = "2016",
month = "2",
day = "16",
doi = "10.1109/IEDM.2015.7409806",
language = "English",
isbn = "9781467398930",
volume = "2016-February",
booktitle = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}