Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Standard

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si. / Berg, Martin; Persson, Karl-Magnus; Kilpi, Olli-Pekka; Svensson, Johannes; Lind, Erik; Wernersson, Lars-Erik.

Technical Digest - International Electron Devices Meeting, IEDM. Vol. 2016-February Institute of Electrical and Electronics Engineers Inc., 2016. 7409806.

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Harvard

Berg, M, Persson, K-M, Kilpi, O-P, Svensson, J, Lind, E & Wernersson, L-E 2016, Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si. in Technical Digest - International Electron Devices Meeting, IEDM. vol. 2016-February, 7409806, Institute of Electrical and Electronics Engineers Inc., 61st IEEE International Electron Devices Meeting, IEDM 2015, Washington, United States, 7-9 December. DOI: 10.1109/IEDM.2015.7409806

APA

Berg, M., Persson, K-M., Kilpi, O-P., Svensson, J., Lind, E., & Wernersson, L-E. (2016). Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si. In Technical Digest - International Electron Devices Meeting, IEDM (Vol. 2016-February). [7409806] Institute of Electrical and Electronics Engineers Inc.. DOI: 10.1109/IEDM.2015.7409806

Vancouver

Berg M, Persson K-M, Kilpi O-P, Svensson J, Lind E, Wernersson L-E. Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si. In Technical Digest - International Electron Devices Meeting, IEDM. Vol. 2016-February. Institute of Electrical and Electronics Engineers Inc.2016. 7409806. Available from, DOI: 10.1109/IEDM.2015.7409806

Author

Berg, Martin; Persson, Karl-Magnus; Kilpi, Olli-Pekka; Svensson, Johannes; Lind, Erik; Wernersson, Lars-Erik / Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si.

Technical Digest - International Electron Devices Meeting, IEDM. Vol. 2016-February Institute of Electrical and Electronics Engineers Inc., 2016. 7409806.

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

RIS

TY - CHAP

T1 - Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

AU - Berg,Martin

AU - Persson,Karl-Magnus

AU - Kilpi,Olli-Pekka

AU - Svensson,Johannes

AU - Lind,Erik

AU - Wernersson,Lars-Erik

PY - 2016/2/16

Y1 - 2016/2/16

N2 - In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.

AB - In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.

U2 - 10.1109/IEDM.2015.7409806

DO - 10.1109/IEDM.2015.7409806

M3 - Paper in conference proceeding

SN - 9781467398930

VL - 2016-February

BT - Technical Digest - International Electron Devices Meeting, IEDM

PB - Institute of Electrical and Electronics Engineers Inc.

ER -