Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
Forskningsoutput: Tidskriftsbidrag › Letter
Abstract
Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.
Detaljer
Författare | |
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Enheter & grupper | |
Forskningsområden | Ämnesklassifikation (UKÄ) – OBLIGATORISK
Nyckelord |
Originalspråk | engelska |
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Sidor (från-till) | 966 - 969 |
Antal sidor | 4 |
Tidskrift | IEEE Electron Device Letters |
Volym | 37 |
Utgivningsnummer | 8 |
Status | Published - 2016 aug 8 |
Peer review utförd | Ja |