Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceeding

Abstract

In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.

Detaljer

Författare
Enheter & grupper
Forskningsområden

Ämnesklassifikation (UKÄ) – OBLIGATORISK

  • Elektroteknik och elektronik
Originalspråkengelska
Titel på värdpublikationTechnical Digest - International Electron Devices Meeting, IEDM
FörlagInstitute of Electrical and Electronics Engineers Inc.
Volym2016-February
ISBN (tryckt)9781467398930
StatusPublished - 2016 feb 16
PublikationskategoriForskning
Peer review utfördJa
Evenemang61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, USA
Varaktighet: 2015 dec 72015 dec 9

Konferens

Konferens61st IEEE International Electron Devices Meeting, IEDM 2015
LandUSA
OrtWashington
Period2015/12/072015/12/09

Nedladdningar

Ingen tillgänglig data