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Personal profile


Erik Larsson received his M.Sc., Tech. Lic, Ph.D, and Docent from Linköping University in 1994, 1998, 2000, 2006,  respectively. He did his Post Doc at the Computer Design and Test Laboratory at Nara Institute of Science and Technology (NAIST), Japan (October 2001-December 2002) , and was through Swedish Foundation for Strategic Research (SSF) (Strategic mobility) at NXP Semiconductors, Eindhoven, The Netherlands (October 2008-May 2010). From 2002 until 2012 he was with Linköping University as an Assistant Professor (2002-2005) and as Associate Professor (2006-2012). He joined Lund University as Associate Professor in 2012. From 2018 he is Professor in Computer Architecture. 

His current research interests include test planning for manufacturing test, test during operation (in-situ), scan-chain diagnosis, silicon debug and validation, IJTAG/SJTAG, stacked 3D chip test, fault-tolerance for MPSoCs (Multi-Processor System-on-Chip), and property checking in distributed systems (MPSOcS with Network-on-Chip (NoC)). He authored the book Introduction to Advanced System-on-Chip Test Design and Optimization (Springer 2005). Erik Larsson is a Senior member of IEEE.

He has received a number of best paper awards: 

He supervised the following awardes theses: 

Some other recognitions:

UKÄ subject classification

  • Computer Systems
  • Embedded Systems
  • Other Electrical Engineering, Electronic Engineering, Information Engineering


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