High-Speed Analog-to-Digital Converters in CMOS

The Analog to Digital (A/D) Converters (ADC) are vital components in high-performance radio devices. In the receiver end, the signal received by the analog front-end can not be directly analyzed by the digital core, thus requiring high-performance ADC circuits acting as bridges connecting the analog and digital domain. These circuits are integrated into Complementary Metal-Oxide-Semiconductor (CMOS) chips, which achieve high performance and consume low power at the same time.
In this research, various types of ADCs are analyzed both in architectural designs and component-level implementations. The goal is to find out optimized circuit designs to be used in high-speed communication devices in the future.
Two Successive-Approximation-Register (SAR) ADCs are studied. One of the SAR ADCs is a previously designed synchronous SAR ADC CMOS chip, implemented in the 22nm Fully Depleted Silicon On Insulator (FD-SOI) CMOS, whose measurement results are shown. An estimation and calibration technique for linearizing its Digital to Analog Converter (DAC) imbalance is presented.
Another SAR ADC is improved from the synchronous version, which has asynchronously clocked internal components, designed and implemented in 22nm FD-SOI. Two Continuous-Time (CT) ΔΣ ADCs were designed and analyzed. One of the ΔΣ ADCs is a high-speed converter implemented in 28nm FD-SOI CMOS, running at 5GHz sampling frequency and targeting at 250MHz signal bandwidth. Another ΔΣ ADC is implemented in 65 nm CMOS and fabricated. It evaluates the effectiveness of digital calibration techniques in linearizing a critical outer-most DAC in the feedback.
All the ADC designs showing in this work are closely related to the state-of-the-art research works. The design specifications from the industry field are also carefully considered during the design phase. The introductions and the design details are explained in the first part of this dissertation, and the relevant research papers are attached in the second part.

Technology advancements in the 21st century create a vast amount of possibilities, allowing us to make strides that our ancestors could only dream of. Communication systems improved greatly in the past several decades. The development of these systems closely follows the evolution of cellular mobile network standards to the latest commercialized 5G: the fifth generation that starts deploying globally. The emerging 5G communication systems enable reliable connections with significantly reduced latency at an increased transmission rate. Communication among people is not limited to voice-only anymore but extended to more versatile formats such as video chat and multimedia message. It is already an essential part of our daily lives: communication among us is through smart devices besides face-to-face.
Nowadays, the rapid development of high-performance handheld devices facilitates fast and secure access to the Internet: a global system that connects people worldwide. We share lives, acquire new knowledge, learn history, and explore the world without leaving home by merely surfing the Internet. The ever increased demands of smooth surfing experiences increase current communication systems’ pressure and bring up the stringent requirements for technology advancement of next-generation communication devices. They prefer low latency, stable and fast upload/download transmission speed, and broad coverage with low energy dissipation.
The advance of communication systems will not be successful without the high-performance Analog to Digital Converter (ADC), an essential component in a modern high-performance radio transceiver device. The ADC acts as a bridge connecting the analog and the digital domain. Usually, the analog domain signals are real-world analog measurable physical quantities, such as voltage or current. However, the high-performance processors are entirely digital and only capable of processing signals in the digital format. High-performance ADCs are capable of immediately digitalizing the analog sig nal at high-speed. A high-speed ADC coping with a high-speed digital processor can digitalize the input analog signals. It allows very flexible, reliable, and highly power-efficient digital signal processing, filtering and calibrating the digital signal in real-time. All the great features are possible thanks to the maturity of Complementary Metal Oxide Semiconductor (CMOS) technology nodes in integrated circuits.
The main focus of this research is designing high-performance ADCs on integrated circuits. This research analyzes various ADC architectures and their component-level implementations in advanced CMOS technologies. This research aims to find optimized designs for high-speed analog-to-digital conversion, understand their benefits and limitations, and evaluate the possibilities of integrating them inside the advanced base station devices in the future. The author performed extensive literature studies to examine the state-of-the-art designs from the research field and industry before the actual circuit designs. The ADC specifications and requirements are carefully drawn up. This dissertation
explains the experimented ADC designs in detail and includes the relevant research papers at the end.