3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI

Hemanth Prabhu; Joachim Rodrigues; Liang Liu; Ove Edfors

doi:10.1109/ISSCC.2017.7870260

3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI

Hemanth Prabhu, Joachim Rodrigues, Liang Liu, Ove Edfors

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

Further exploitation of the spatial domain, as in Massive MIMO (MaMi) systems, is imperative to meet future communication requirements [1]. Up-scaling of conventional 4×4 small-scale MIMO implementations to MaMi is prohibitive in-terms of flexibility, as well as area and power cost. This work discloses a 1.1mm² 128×8 MaMi baseband chip, achieving up to 12dB array and 2× spatial multiplexing gains. The area cost compared to previous state-of-the-art MIMO implementations [2-3], is reduced by 53% and 17% for up- and down-link, respectively. Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.

Original language	English
Title of host publication	2017 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	60-61
Number of pages	2
Volume	60
ISBN (Electronic)	978-1-5090-3758-2
ISBN (Print)	978-1-5090-3759-9
DOIs	https://doi.org/10.1109/ISSCC.2017.7870260
Publication status	Published - 2017
Event	64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States Duration: 2017 Feb 5 → 2017 Feb 9

Conference

Conference	64th IEEE International Solid-State Circuits Conference, ISSCC 2017
Country/Territory	United States
City	San Francisco
Period	2017/02/05 → 2017/02/09

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Subject classification (UKÄ)

Signal Processing
Other Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

Massive MIMO
ASIC implementation

Access to Document

10.1109/ISSCC.2017.7870260

Cite this

@inproceedings{5c811b1dbfe44d50904c266a9b23d5a4,

title = "3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI",

abstract = "Further exploitation of the spatial domain, as in Massive MIMO (MaMi) systems, is imperative to meet future communication requirements [1]. Up-scaling of conventional 4×4 small-scale MIMO implementations to MaMi is prohibitive in-terms of flexibility, as well as area and power cost. This work discloses a 1.1mm2 128×8 MaMi baseband chip, achieving up to 12dB array and 2× spatial multiplexing gains. The area cost compared to previous state-of-the-art MIMO implementations [2-3], is reduced by 53\% and 17\% for up- and down-link, respectively. Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.",

keywords = "Massive MIMO, ASIC implementation",

author = "Hemanth Prabhu and Joachim Rodrigues and Liang Liu and Ove Edfors",

year = "2017",

doi = "10.1109/ISSCC.2017.7870260",

language = "English",

isbn = "978-1-5090-3759-9",

volume = "60",

pages = "60--61",

booktitle = "2017 IEEE International Solid-State Circuits Conference (ISSCC)",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "64th IEEE International Solid-State Circuits Conference, ISSCC 2017 ; Conference date: 05-02-2017 Through 09-02-2017",

}

Prabhu, H, Rodrigues, J , Liu, L & Edfors, O 2017, 3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI. in 2017 IEEE International Solid-State Circuits Conference (ISSCC). vol. 60, 7870260, IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 60-61, 64th IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, United States, 2017/02/05. https://doi.org/10.1109/ISSCC.2017.7870260

3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI. / Prabhu, Hemanth; Rodrigues, Joachim ; Liu, Liang et al.
2017 IEEE International Solid-State Circuits Conference (ISSCC). Vol. 60 IEEE - Institute of Electrical and Electronics Engineers Inc., 2017. p. 60-61 7870260.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - 3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI

AU - Prabhu, Hemanth

AU - Rodrigues, Joachim

AU - Liu, Liang

AU - Edfors, Ove

PY - 2017

Y1 - 2017

N2 - Further exploitation of the spatial domain, as in Massive MIMO (MaMi) systems, is imperative to meet future communication requirements [1]. Up-scaling of conventional 4×4 small-scale MIMO implementations to MaMi is prohibitive in-terms of flexibility, as well as area and power cost. This work discloses a 1.1mm2 128×8 MaMi baseband chip, achieving up to 12dB array and 2× spatial multiplexing gains. The area cost compared to previous state-of-the-art MIMO implementations [2-3], is reduced by 53% and 17% for up- and down-link, respectively. Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.

AB - Further exploitation of the spatial domain, as in Massive MIMO (MaMi) systems, is imperative to meet future communication requirements [1]. Up-scaling of conventional 4×4 small-scale MIMO implementations to MaMi is prohibitive in-terms of flexibility, as well as area and power cost. This work discloses a 1.1mm2 128×8 MaMi baseband chip, achieving up to 12dB array and 2× spatial multiplexing gains. The area cost compared to previous state-of-the-art MIMO implementations [2-3], is reduced by 53% and 17% for up- and down-link, respectively. Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.

KW - Massive MIMO

KW - ASIC implementation

UR - https://www.scopus.com/pages/publications/85016247022

U2 - 10.1109/ISSCC.2017.7870260

DO - 10.1109/ISSCC.2017.7870260

M3 - Paper in conference proceeding

AN - SCOPUS:85016247022

SN - 978-1-5090-3759-9

VL - 60

SP - 60

EP - 61

BT - 2017 IEEE International Solid-State Circuits Conference (ISSCC)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 64th IEEE International Solid-State Circuits Conference, ISSCC 2017

Y2 - 5 February 2017 through 9 February 2017

ER -

3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI

Abstract

Conference

UN SDGs

Subject classification (UKÄ)

Free keywords

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