60 GHz Second Harmonic Power Amplifiers in 130-nm CMOS

Johan Wernehag; Henrik Sjöland

60 GHz Second Harmonic Power Amplifiers in 130-nm CMOS

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding

Abstract

Abstract—Two different frequency doubling power amplifiers have been measured, one with differential and one with single-ended input, both with single-ended output at 60 GHz. The amplifiers have been implemented in a 1p8M 130-nm CMOS process. The resonant nodes are tuned to 30 GHz or 60 GHz using on-chip transmission lines, which have been simulated in ADS and Momentum.

The measured input impedance of the single-ended PA is high at 250 Ω, and the differential input is similar, making the PA a suitable load for an oscillator in a fully integrated transmitter. The single-ended and differential input PA delivers 1 dBm and 3 dBm, respectively, of measured saturated output power to 50 Ω, both with a drain efficiency of 8%

Original language	English
Title of host publication	Proceedings of Swedish System-on-Chip Conference (SSoCC)
Pages	1-4
Number of pages	4
Publication status	Published - 2008
Event	Swedish System-on-Chip Conference 2008 (SSoCC’08) - Gnesta, Gnesta, Sweden Duration: 2008 May 5 → 2008 May 6

Conference

Conference	Swedish System-on-Chip Conference 2008 (SSoCC’08)
Country/Territory	Sweden
City	Gnesta
Period	2008/05/05 → 2008/05/06

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Cite this

@inproceedings{b81ca6c04bca406abd16a07dc5f5b683,

title = "60 GHz Second Harmonic Power Amplifiers in 130-nm CMOS",

abstract = "Abstract—Two different frequency doubling power amplifiers have been measured, one with differential and one with single-ended input, both with single-ended output at 60 GHz. The amplifiers have been implemented in a 1p8M 130-nm CMOS process. The resonant nodes are tuned to 30 GHz or 60 GHz using on-chip transmission lines, which have been simulated in ADS and Momentum. The measured input impedance of the single-ended PA is high at 250 Ω, and the differential input is similar, making the PA a suitable load for an oscillator in a fully integrated transmitter. The single-ended and differential input PA delivers 1 dBm and 3 dBm, respectively, of measured saturated output power to 50 Ω, both with a drain efficiency of 8\%",

author = "Johan Wernehag and Henrik Sj{\"o}land",

year = "2008",

language = "English",

pages = "1--4",

booktitle = "Proceedings of Swedish System-on-Chip Conference (SSoCC)",

note = "Swedish System-on-Chip Conference 2008 (SSoCC{\textquoteright}08) ; Conference date: 05-05-2008 Through 06-05-2008",

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TY - GEN

T1 - 60 GHz Second Harmonic Power Amplifiers in 130-nm CMOS

AU - Wernehag, Johan

AU - Sjöland, Henrik

PY - 2008

Y1 - 2008

N2 - Abstract—Two different frequency doubling power amplifiers have been measured, one with differential and one with single-ended input, both with single-ended output at 60 GHz. The amplifiers have been implemented in a 1p8M 130-nm CMOS process. The resonant nodes are tuned to 30 GHz or 60 GHz using on-chip transmission lines, which have been simulated in ADS and Momentum. The measured input impedance of the single-ended PA is high at 250 Ω, and the differential input is similar, making the PA a suitable load for an oscillator in a fully integrated transmitter. The single-ended and differential input PA delivers 1 dBm and 3 dBm, respectively, of measured saturated output power to 50 Ω, both with a drain efficiency of 8%

AB - Abstract—Two different frequency doubling power amplifiers have been measured, one with differential and one with single-ended input, both with single-ended output at 60 GHz. The amplifiers have been implemented in a 1p8M 130-nm CMOS process. The resonant nodes are tuned to 30 GHz or 60 GHz using on-chip transmission lines, which have been simulated in ADS and Momentum. The measured input impedance of the single-ended PA is high at 250 Ω, and the differential input is similar, making the PA a suitable load for an oscillator in a fully integrated transmitter. The single-ended and differential input PA delivers 1 dBm and 3 dBm, respectively, of measured saturated output power to 50 Ω, both with a drain efficiency of 8%

M3 - Paper in conference proceeding

SP - 1

EP - 4

BT - Proceedings of Swedish System-on-Chip Conference (SSoCC)

T2 - Swedish System-on-Chip Conference 2008 (SSoCC’08)

Y2 - 5 May 2008 through 6 May 2008

ER -

60 GHz Second Harmonic Power Amplifiers in 130-nm CMOS

Abstract

Conference

Subject classification (UKÄ)

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Cite this