A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS

Babak Mohammadi; Oskar Andersson; Pascal Meinerzhagen; Syed Muhammad Yasser Sherazi; Andreas Burg; Joachim Rodrigues

doi:10.1109/FTFC.2014.6828618

A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS

Babak Mohammadi, Oskar Andersson, Pascal Meinerzhagen, Syed Muhammad Yasser Sherazi, Andreas Burg, Joachim Rodrigues

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280 mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power

Original language	English
Title of host publication	[Host publication title missing]
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
DOIs	https://doi.org/10.1109/FTFC.2014.6828618
Publication status	Published - 2014
Event	FTFC - Monaco, Monaco Duration: 2014 May 4 → 2014 May 6

Conference

Conference	FTFC
Country/Territory	Monaco
Period	2014/05/04 → 2014/05/06

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/FTFC.2014.6828618

Cite this

@inproceedings{7459b1a81e754ea48c0eeba79c76d4f7,

title = "A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS",

abstract = "The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280 mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power",

author = "Babak Mohammadi and Oskar Andersson and Pascal Meinerzhagen and Sherazi, {Syed Muhammad Yasser} and Andreas Burg and Joachim Rodrigues",

year = "2014",

doi = "10.1109/FTFC.2014.6828618",

language = "English",

booktitle = "[Host publication title missing]",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "FTFC ; Conference date: 04-05-2014 Through 06-05-2014",

}

TY - GEN

T1 - A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS

AU - Mohammadi, Babak

AU - Andersson, Oskar

AU - Meinerzhagen, Pascal

AU - Sherazi, Syed Muhammad Yasser

AU - Burg, Andreas

AU - Rodrigues, Joachim

PY - 2014

Y1 - 2014

N2 - The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280 mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power

AB - The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280 mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power

U2 - 10.1109/FTFC.2014.6828618

DO - 10.1109/FTFC.2014.6828618

M3 - Paper in conference proceeding

BT - [Host publication title missing]

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - FTFC

Y2 - 4 May 2014 through 6 May 2014

ER -

A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS

Abstract

Conference

Subject classification (UKÄ)

Access to Document

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Cite this