A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS

Cheng Chen; Jiren Yuan

doi:10.1109/ISCAS.2007.377923

A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS

Cheng Chen, Jiren Yuan

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (>250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Sepctre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm<sup>2</sup>. © 2007 IEEE.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	1709-1712
DOIs	https://doi.org/10.1109/ISCAS.2007.377923
Publication status	Published - 2007
Event	2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States Duration: 2007 May 27 → 2007 May 30

Publication series

Name
ISSN (Print)	2158-1525
ISSN (Electronic)	0271-4310

Conference

Conference	2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
Country/Territory	United States
City	New Orleans, LA
Period	2007/05/27 → 2007/05/30

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

Preprocessing blocks
Auto-zero calibration
Wide input bandwidth
Sepctre simulation

Access to Document

10.1109/ISCAS.2007.377923

Cite this

@inproceedings{ae0dc4e2421049519f7e13cefac6618d,

title = "A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS",

abstract = "A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (>250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Sepctre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm2. {\textcopyright} 2007 IEEE.",

keywords = "Preprocessing blocks, Auto-zero calibration, Wide input bandwidth, Sepctre simulation",

author = "Cheng Chen and Jiren Yuan",

year = "2007",

doi = "10.1109/ISCAS.2007.377923",

language = "English",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

pages = "1709--1712",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

address = "United States",

note = "2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 ; Conference date: 27-05-2007 Through 30-05-2007",

}

Chen, C & Yuan, J 2007, A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS. in Proceedings - IEEE International Symposium on Circuits and Systems. IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 1709-1712, 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, United States, 2007/05/27. https://doi.org/10.1109/ISCAS.2007.377923

TY - GEN

T1 - A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS

AU - Chen, Cheng

AU - Yuan, Jiren

PY - 2007

Y1 - 2007

N2 - A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (>250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Sepctre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm2. © 2007 IEEE.

AB - A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (>250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Sepctre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm2. © 2007 IEEE.

KW - Preprocessing blocks

KW - Auto-zero calibration

KW - Wide input bandwidth

KW - Sepctre simulation

U2 - 10.1109/ISCAS.2007.377923

DO - 10.1109/ISCAS.2007.377923

M3 - Paper in conference proceeding

SP - 1709

EP - 1712

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007

Y2 - 27 May 2007 through 30 May 2007

ER -

A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS

Abstract

Publication series

Conference

Subject classification (UKÄ)

Free keywords

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