A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS

Syed Muhammad Yasser Sherazi; Peter Nilsson; Henrik Sjöland; Joachim Rodrigues

doi:10.1109/ICECS.2012.6463654

A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS

Syed Muhammad Yasser Sherazi, Peter Nilsson, Henrik Sjöland, Joachim Rodrigues

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

Measurements of a sub-threshold (sub-VT) decimation
filter, composed of four half band digital (HBD) filters in
65 nm CMOS are presented. Different unfolded architectures are
analyzed and implemented to combat speed degradation. The
architectures are analyzed for throughput and energy efficiency
over several threshold options. Reliability in the sub-VT domain
is analyzed by Monte-Carlo simulations. The simulation results
are validated by measurements and demonstrate that low-power
standard threshold logic (LP-SVT) and different architectural
flavors are suitable for a low-power implementation. Silicon
measurements prove functionality down to 350mV supply, with
a maximum clock frequency of 500 kHz, having an energy
dissipation of 102 fJ/cycle.

Original language	English
Title of host publication	19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	978-1-4673-1261-5
ISBN (Print)	978-1-4673-1261-5
DOIs	https://doi.org/10.1109/ICECS.2012.6463654
Publication status	Published - 2012
Event	IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012 - Seville, Spain Duration: 2012 Dec 9 → 2012 Dec 12

Conference

Conference	IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012
Country/Territory	Spain
City	Seville
Period	2012/12/09 → 2012/12/12

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

energy dissipation
measurements
sub-threshold
half band digital (HBD) filters
65 nm CMOS
and architectures.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ICECS.2012.6463654

Cite this

@inproceedings{735747da31f649ad85baff05edd0a26e,

title = "A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS",

abstract = "Measurements of a sub-threshold (sub-VT) decimation filter, composed of four half band digital (HBD) filters in 65 nm CMOS are presented. Different unfolded architectures are analyzed and implemented to combat speed degradation. The architectures are analyzed for throughput and energy efficiency over several threshold options. Reliability in the sub-VT domain is analyzed by Monte-Carlo simulations. The simulation results are validated by measurements and demonstrate that low-power standard threshold logic (LP-SVT) and different architectural flavors are suitable for a low-power implementation. Silicon measurements prove functionality down to 350mV supply, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle.",

keywords = "energy dissipation, measurements, sub-threshold, half band digital (HBD) filters, 65 nm CMOS, and architectures.",

author = "Sherazi, {Syed Muhammad Yasser} and Peter Nilsson and Henrik Sj{\"o}land and Joachim Rodrigues",

year = "2012",

doi = "10.1109/ICECS.2012.6463654",

language = "English",

isbn = "978-1-4673-1261-5 ",

booktitle = "19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012 ; Conference date: 09-12-2012 Through 12-12-2012",

}

Sherazi, SMY, Nilsson, P, Sjöland, H & Rodrigues, J 2012, A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS. in 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012). IEEE - Institute of Electrical and Electronics Engineers Inc., IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012, Seville, Spain, 2012/12/09. https://doi.org/10.1109/ICECS.2012.6463654

A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS. / Sherazi, Syed Muhammad Yasser; Nilsson, Peter; Sjöland, Henrik et al.
19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012). IEEE - Institute of Electrical and Electronics Engineers Inc., 2012.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS

AU - Sherazi, Syed Muhammad Yasser

AU - Nilsson, Peter

AU - Sjöland, Henrik

AU - Rodrigues, Joachim

PY - 2012

Y1 - 2012

N2 - Measurements of a sub-threshold (sub-VT) decimation filter, composed of four half band digital (HBD) filters in 65 nm CMOS are presented. Different unfolded architectures are analyzed and implemented to combat speed degradation. The architectures are analyzed for throughput and energy efficiency over several threshold options. Reliability in the sub-VT domain is analyzed by Monte-Carlo simulations. The simulation results are validated by measurements and demonstrate that low-power standard threshold logic (LP-SVT) and different architectural flavors are suitable for a low-power implementation. Silicon measurements prove functionality down to 350mV supply, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle.

AB - Measurements of a sub-threshold (sub-VT) decimation filter, composed of four half band digital (HBD) filters in 65 nm CMOS are presented. Different unfolded architectures are analyzed and implemented to combat speed degradation. The architectures are analyzed for throughput and energy efficiency over several threshold options. Reliability in the sub-VT domain is analyzed by Monte-Carlo simulations. The simulation results are validated by measurements and demonstrate that low-power standard threshold logic (LP-SVT) and different architectural flavors are suitable for a low-power implementation. Silicon measurements prove functionality down to 350mV supply, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle.

KW - energy dissipation

KW - measurements

KW - sub-threshold

KW - half band digital (HBD) filters

KW - 65 nm CMOS

KW - and architectures.

U2 - 10.1109/ICECS.2012.6463654

DO - 10.1109/ICECS.2012.6463654

M3 - Paper in conference proceeding

SN - 978-1-4673-1261-5

BT - 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012

Y2 - 9 December 2012 through 12 December 2012

ER -

A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS

Abstract

Conference

Subject classification (UKÄ)

Free keywords

UN SDGs

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Cite this