A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL

Ying Wu, Ping Lu, Robert Bogdan Staszewski

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

Abstract

A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.
Original languageEnglish
Title of host publication 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages95-98
ISBN (Electronic)978-1-4799-7642-3
DOIs
Publication statusPublished - 2015
EventIEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015 - Phoenix, Arizona, United States
Duration: 2015 May 172015 May 19

Conference

ConferenceIEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015
Country/TerritoryUnited States
CityPhoenix, Arizona
Period2015/05/172015/05/19

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Fingerprint

Dive into the research topics of 'A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL'. Together they form a unique fingerprint.

Cite this