Abstract
A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.
Original language | English |
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Title of host publication | 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) |
Publisher | IEEE - Institute of Electrical and Electronics Engineers Inc. |
Pages | 95-98 |
ISBN (Electronic) | 978-1-4799-7642-3 |
DOIs | |
Publication status | Published - 2015 |
Event | IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015 - Phoenix, Arizona, United States Duration: 2015 May 17 → 2015 May 19 |
Conference
Conference | IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015 |
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Country/Territory | United States |
City | Phoenix, Arizona |
Period | 2015/05/17 → 2015/05/19 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering