A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL

Ying Wu; Ping Lu; Robert Bogdan Staszewski

doi:10.1109/RFIC.2015.7337713

A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL

Ying Wu, Ping Lu, Robert Bogdan Staszewski

Department of Electrical and Information Technology

Delft University of Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.

Original language	English
Title of host publication	2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	95-98
ISBN (Electronic)	978-1-4799-7642-3
DOIs	https://doi.org/10.1109/RFIC.2015.7337713
Publication status	Published - 2015
Event	IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015 - Phoenix, Arizona, United States Duration: 2015 May 17 → 2015 May 19

Conference

Conference	IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015
Country/Territory	United States
City	Phoenix, Arizona
Period	2015/05/17 → 2015/05/19

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/RFIC.2015.7337713

Cite this

@inproceedings{1555f3506496471f98f9ebab25f1bc9f,

title = "A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL",

abstract = "A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.",

author = "Ying Wu and Ping Lu and Staszewski, {Robert Bogdan}",

year = "2015",

doi = "10.1109/RFIC.2015.7337713",

language = "English",

pages = "95--98",

booktitle = "2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015 ; Conference date: 17-05-2015 Through 19-05-2015",

}

Wu, Y, Lu, P & Staszewski, RB 2015, A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL. in 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 95-98, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, Phoenix, Arizona, United States, 2015/05/17. https://doi.org/10.1109/RFIC.2015.7337713

A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL. / Wu, Ying; Lu, Ping; Staszewski, Robert Bogdan.
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE - Institute of Electrical and Electronics Engineers Inc., 2015. p. 95-98.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

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AU - Lu, Ping

AU - Staszewski, Robert Bogdan

PY - 2015

Y1 - 2015

N2 - A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.

AB - A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.

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DO - 10.1109/RFIC.2015.7337713

M3 - Paper in conference proceeding

SP - 95

EP - 98

BT - 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015

Y2 - 17 May 2015 through 19 May 2015

ER -

A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL

Abstract

Conference

Subject classification (UKÄ)

Access to Document

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Cite this