Abstract
Distributed massive multiple-input multiple-output (D-MIMO) has been identified as a promising technology to meet the service requirements of 6 G wireless networks and beyond. The coordination between a massive number of distributed antennas introduces stiff challenges and requires a substantial amount of computing resources that must be put together with careful algorithm-architecture codesign. The process places a premium on flexibility, and toward this end the current paper presents an application-specific instruction set processor (ASIP) utilizing single instruction multiple data (SIMD), allied with programmer-visible hardware accelerators and a specialized memory subsystem, and employed in distributed and scalable massive MIMO systems. The chip is fabricated using the GF22nm FDX technology.
| Original language | English |
|---|---|
| Title of host publication | ESSERC 2024 - Proceedings |
| Subtitle of host publication | 50th IEEE European Solid-State Electronics Research Conference |
| Publisher | IEEE Computer Society |
| Pages | 257-260 |
| Number of pages | 4 |
| ISBN (Electronic) | 9798350388138 |
| DOIs | |
| Publication status | Published - 2024 |
| Event | 50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024 - Bruges, Belgium Duration: 2024 Sept 9 → 2024 Sept 12 |
Conference
| Conference | 50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024 |
|---|---|
| Country/Territory | Belgium |
| City | Bruges |
| Period | 2024/09/09 → 2024/09/12 |
Subject classification (UKÄ)
- Computer Engineering
Free keywords
- baseband ASIP
- Distributed massive MIMO
- Golub-Kahan
- matrix decomposition
- RISC-V
- SIMD
- SVD accelerator
- systolic array