A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28 nm FD–SOI

A 128kb ultra-low voltage SRAM, based on a leakage optimized single-WELL 7T bitcell in 28 nm FD–SOI technology is presented. An ideal power management scenario in a single supply system is achieved by permanently keeping the storage elements in the vicinity of the retention voltage. Performance and reliability is regained by boosting the voltage on critical nodes. The cost of voltage boost generation unit is minimized by 66 low-power and area efficient on-chip charge
pumps, i.e., 64 for boosting the voltages on write-bitlines and 2 for the wordlines. The charge pump energy overhead is reduced by introducing a new boost paradigm with an on-demand activation mechanism that generates the required boost level in a single clock cycle. A sense amplifier-less read architecture enables a reliable and high performance read operation. Measurements identify several meritorious metrics. The minimum read energy is identified as 8.4fJ/bit-access, achieved for 90 MHz operation at
0.3 V. Furthermore, the minimum operating voltage is measured
as 240 mV, and data is retained in ultra-low voltage regime,
ranging down to 0.2V. The bitcell area, implemented using
standard design rules, is 0.261µm2. The entire memory, including
the digital test circuitry, occupies 0.161 mm2 of chip area.