A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI

Babak Mohammadi; Oskar Andersson; Joseph Nguyen; Lorenzo Ciampolini; Andreia Cathelin; Joachim Rodrigues

doi:10.1109/ESSCIRC.2016.7598333

A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI

Babak Mohammadi, Oskar Andersson, Joseph Nguyen, Lorenzo Ciampolini, Andreia Cathelin, Joachim Rodrigues

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90 MHz read speed at 300 mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240 mV and the retention voltage is found at 200 mV.

Original language	English
Title of host publication	European Solid-State Circuits Conference (ESSCIRC), 2016
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	978-1-5090-2972-3
DOIs	https://doi.org/10.1109/ESSCIRC.2016.7598333
Publication status	Published - 2016
Event	European Solid-State Circuits Conference (ESSCIRC). 2016 - Lausanne, Switzerland Duration: 2016 Sept 12 → 2016 Sept 15

Conference

Conference	European Solid-State Circuits Conference (ESSCIRC). 2016
Country/Territory	Switzerland
City	Lausanne
Period	2016/09/12 → 2016/09/15

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ESSCIRC.2016.7598333

1 Doctoral Thesis (compilation)

Ultra-low Power Design Approaches in Memories and Assist Techniques
Mohammadi, B., 2017, Department of Electrical and Information Technology, Lund University. 186 p.
Research output: Thesis › Doctoral Thesis (compilation)

Cite this

Mohammadi, B., Andersson, O., Nguyen, J., Ciampolini, L., Cathelin, A., & Rodrigues, J. (2016). A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI. In European Solid-State Circuits Conference (ESSCIRC), 2016 Article 16408290 IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC.2016.7598333

@inproceedings{0464838f343f4fdeaa0494af04369124,

title = "A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI",

abstract = "In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90 MHz read speed at 300 mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240 mV and the retention voltage is found at 200 mV. ",

author = "Babak Mohammadi and Oskar Andersson and Joseph Nguyen and Lorenzo Ciampolini and Andreia Cathelin and Joachim Rodrigues",

year = "2016",

doi = "10.1109/ESSCIRC.2016.7598333",

language = "English",

booktitle = "European Solid-State Circuits Conference (ESSCIRC), 2016",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = " European Solid-State Circuits Conference (ESSCIRC). 2016 ; Conference date: 12-09-2016 Through 15-09-2016",

}

Mohammadi, B, Andersson, O, Nguyen, J, Ciampolini, L, Cathelin, A & Rodrigues, J 2016, A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI. in European Solid-State Circuits Conference (ESSCIRC), 2016., 16408290 , IEEE - Institute of Electrical and Electronics Engineers Inc., European Solid-State Circuits Conference (ESSCIRC). 2016, Lausanne, Switzerland, 2016/09/12. https://doi.org/10.1109/ESSCIRC.2016.7598333

A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI. / Mohammadi, Babak; Andersson, Oskar; Nguyen, Joseph et al.
European Solid-State Circuits Conference (ESSCIRC), 2016. IEEE - Institute of Electrical and Electronics Engineers Inc., 2016. 16408290 .

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI

AU - Mohammadi, Babak

AU - Andersson, Oskar

AU - Nguyen, Joseph

AU - Ciampolini, Lorenzo

AU - Cathelin, Andreia

AU - Rodrigues, Joachim

PY - 2016

Y1 - 2016

N2 - In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90 MHz read speed at 300 mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240 mV and the retention voltage is found at 200 mV.

AB - In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90 MHz read speed at 300 mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240 mV and the retention voltage is found at 200 mV.

U2 - 10.1109/ESSCIRC.2016.7598333

DO - 10.1109/ESSCIRC.2016.7598333

M3 - Paper in conference proceeding

BT - European Solid-State Circuits Conference (ESSCIRC), 2016

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - European Solid-State Circuits Conference (ESSCIRC). 2016

Y2 - 12 September 2016 through 15 September 2016

ER -

A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI

Abstract

Conference

Subject classification (UKÄ)

UN SDGs

Access to Document

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Research output

Ultra-low Power Design Approaches in Memories and Assist Techniques

Cite this