A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI

Mattias Palm, Daniele Mastantuono, Roland Strandberg, Lars Sundström, Sven Mattisson

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

2 Citations (SciVal)

Abstract

This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective subADC voltage reference. The prototype is implemented in 28 nm FD-SOI and achieves an SNR/SNDR/SFDR/FOM of 56.9/56.1/65/154 dB, consuming 89 mW including input buffer, voltage references, bias with bandgap and clock circuitry.
Original languageEnglish
Title of host publicationESSCIRC 2017
Subtitle of host publication43rd IEEE European Solid State Circuits Conference
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)978-1-5090-5025-3
ISBN (Print)978-1-5090-5026-0
DOIs
Publication statusPublished - 2017
Externally publishedYes
Event43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017 - Leuven, Belgium
Duration: 2017 Sep 112017 Sep 14

Conference

Conference43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017
Country/TerritoryBelgium
CityLeuven
Period2017/09/112017/09/14

Subject classification (UKÄ)

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • buffer linearization
  • time-interleaved pipelined-SAR converter
  • multiband mobile communication receiver
  • super-source follower
  • drain bias resistor
  • sampling time mismatch
  • SFDR
  • gain mismatch correction
  • FD-SOI
  • input buffer
  • TI pipelined-SAR converter
  • specific bias current
  • common sample and hold circuit
  • SNR
  • SNDR
  • FOM
  • voltage references
  • bandgap
  • clock circuitry
  • subADC voltage reference

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