A 1.8V transmitter for 10/100 Mbps Ethernet physical layer

Cheng Tao; Li Yang; Ning Li; Ping Lu

doi:10.1109/ICASIC.2005.1611349

A 1.8V transmitter for 10/100 Mbps Ethernet physical layer

Cheng Tao, Li Yang, Ning Li, Ping Lu

External Organization - Unknown

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A 0.18 mum 1.8 V CMOS transmitter for 10/100Mbps Ethernet physical layer standards is described in this paper. The circuit is substantively a current-steering digital-to-analog converter with 5-bit resolution, 125MHz sample rate and 4ns transition time. A novel latch circuit is designed, as well as a structure is provided to realize the accurate rise/fall time control of waveform

Original language	English
Title of host publication	[Host publication title missing]
Pages	415-418
DOIs	https://doi.org/10.1109/ICASIC.2005.1611349
Publication status	Published - 2005
Externally published	Yes
Event	The 6th International Conference on ASIC, ASICON 2005 - Shanghai, China Duration: 2005 Oct 24 → 2005 Oct 27

Conference

Conference	The 6th International Conference on ASIC, ASICON 2005
Country/Territory	China
City	Shanghai
Period	2005/10/24 → 2005/10/27

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/ICASIC.2005.1611349

Cite this

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title = "A 1.8V transmitter for 10/100 Mbps Ethernet physical layer",

abstract = "A 0.18 mum 1.8 V CMOS transmitter for 10/100Mbps Ethernet physical layer standards is described in this paper. The circuit is substantively a current-steering digital-to-analog converter with 5-bit resolution, 125MHz sample rate and 4ns transition time. A novel latch circuit is designed, as well as a structure is provided to realize the accurate rise/fall time control of waveform",

author = "Cheng Tao and Li Yang and Ning Li and Ping Lu",

year = "2005",

doi = "10.1109/ICASIC.2005.1611349",

language = "English",

isbn = "0-7803-9210-8",

pages = "415--418",

booktitle = "[Host publication title missing]",

note = "The 6th International Conference on ASIC, ASICON 2005 ; Conference date: 24-10-2005 Through 27-10-2005",

}

TY - GEN

T1 - A 1.8V transmitter for 10/100 Mbps Ethernet physical layer

AU - Tao, Cheng

AU - Yang, Li

AU - Li, Ning

AU - Lu, Ping

PY - 2005

Y1 - 2005

N2 - A 0.18 mum 1.8 V CMOS transmitter for 10/100Mbps Ethernet physical layer standards is described in this paper. The circuit is substantively a current-steering digital-to-analog converter with 5-bit resolution, 125MHz sample rate and 4ns transition time. A novel latch circuit is designed, as well as a structure is provided to realize the accurate rise/fall time control of waveform

AB - A 0.18 mum 1.8 V CMOS transmitter for 10/100Mbps Ethernet physical layer standards is described in this paper. The circuit is substantively a current-steering digital-to-analog converter with 5-bit resolution, 125MHz sample rate and 4ns transition time. A novel latch circuit is designed, as well as a structure is provided to realize the accurate rise/fall time control of waveform

U2 - 10.1109/ICASIC.2005.1611349

DO - 10.1109/ICASIC.2005.1611349

M3 - Paper in conference proceeding

SN - 0-7803-9210-8

SP - 415

EP - 418

BT - [Host publication title missing]

T2 - The 6th International Conference on ASIC, ASICON 2005

Y2 - 24 October 2005 through 27 October 2005

ER -

A 1.8V transmitter for 10/100 Mbps Ethernet physical layer

Abstract

Conference

Subject classification (UKÄ)

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Cite this