A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS

Mohammed Abdulaziz, Muhammed Shakir, Ping Lu, Pietro Andreani

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

1 Citation (SciVal)

Abstract

A divider-less all digital phase locked loop (ADPLL) with a high frequency resolution is implemented. All blocks excluding digitally controlled oscillator (DCO) and time to digital converter (TDC) are realized in standard digital design which consumes less power. The DCO core adopts an improved source-varactor LC resonant tank to achieve a 20KHz frequency resolution. With the help of an additional ΔΣ modulator, the final frequency resolution is 625Hz. This work is simulated in 90nm CMOS process technology and consumes 7.6mW (DCO occupies 97.4%) under the power supply of 1.2V.
Original languageEnglish
Title of host publication[Host publication title missing]
Number of pages4
DOIs
Publication statusPublished - 2011
Event29th Norchip conference, 2011 - Lund, Lund, Sweden
Duration: 2011 Nov 142011 Nov 15

Conference

Conference29th Norchip conference, 2011
Country/TerritorySweden
CityLund
Period2011/11/142011/11/15

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • voltage 1.2 V
  • time to digital converter
  • standard digital design
  • source-varactor LC resonant tank
  • size 90 nm
  • power 7.6 mW
  • high frequency resolution
  • frequency 625 GHz
  • frequency 20 kHz
  • frequency 2.7 GHz
  • divider-less all digital phase-locked loop
  • digitally controlled oscillator
  • delta sigma modulator
  • CMOS process technology

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