Abstract
Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS process and consumes 3mA from 1.2V when operating at 25MHz. The native Vernier resolution of the TDC is 5.8ps, while the total noise integrated over a bandwidth of 800kHz yields an equivalent TDC resolution of 3.2ps.
| Original language | English |
|---|---|
| Pages (from-to) | 1626-1635 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 47 |
| Issue number | 7 |
| Publication status | Published - 2012 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- Gated Ring Oscillator
- Time-to-Digital Converter
- Vernier Delay Line
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