A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS

Therese Forsberg; Johan Wernehag; Henrik Sjöland; Markus Törmänen

doi:10.1109/NORCHIP.2018.8573468

A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS

Therese Forsberg, Johan Wernehag, Henrik Sjöland, Markus Törmänen

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A mm-wave divide-by-two circuit with high injection efficiency, implemented in a 28-nm fully-depleted silicon-on-insulator (FD-SOI) CMOS process is demonstrated stand-alone, as well as using an on-chip voltage controlled oscillator (VCO) as the input signal source. Measurements show that the divider has a 30.1 % tuning range centered at an output frequency of 24 GHz, at an input signal power of -1.5 dBm, and a power consumption of 4.3 mW from a 0.9 V supply. The VCO and divider combination has a tuning range of 10.2 %, centered at an output frequency of 30.2 GHz, at a total power consumption of 6.3 mW, and an output phase noise of -111 dBc/Hz at 10 MHz offset. The active area of the divider is 0.032 mm 2 and of the divider and VCO combination 0.043 mm 2 .

Original language	English
Title of host publication	2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Number of pages	4
ISBN (Electronic)	978-1-5386-7656-1
ISBN (Print)	978-1-5386-7657-8
DOIs	https://doi.org/10.1109/NORCHIP.2018.8573468
Publication status	Published - 2018 Oct 30
Event	2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) - Tallin, Estonia Duration: 2018 Oct 30 → 2018 Oct 31

Conference

Conference	2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
Country/Territory	Estonia
City	Tallin
Period	2018/10/30 → 2018/10/31

Subject classification (UKÄ)

Other Electrical Engineering, Electronic Engineering, Information Engineering

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10.1109/NORCHIP.2018.8573468

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Forsberg, T., Wernehag, J., Sjöland, H., & Törmänen, M. (2018). A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS. In 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NORCHIP.2018.8573468

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title = "A 4.3-mW mm-Wave Divide-by-Two Circuit with 30\% Locking Range in 28-nm FD-SOI CMOS",

abstract = "A mm-wave divide-by-two circuit with high injection efficiency, implemented in a 28-nm fully-depleted silicon-on-insulator (FD-SOI) CMOS process is demonstrated stand-alone, as well as using an on-chip voltage controlled oscillator (VCO) as the input signal source. Measurements show that the divider has a 30.1 \% tuning range centered at an output frequency of 24 GHz, at an input signal power of -1.5 dBm, and a power consumption of 4.3 mW from a 0.9 V supply. The VCO and divider combination has a tuning range of 10.2 \%, centered at an output frequency of 30.2 GHz, at a total power consumption of 6.3 mW, and an output phase noise of -111 dBc/Hz at 10 MHz offset. The active area of the divider is 0.032 mm 2 and of the divider and VCO combination 0.043 mm 2 .",

author = "Therese Forsberg and Johan Wernehag and Henrik Sj{\"o}land and Markus T{\"o}rm{\"a}nen",

year = "2018",

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doi = "10.1109/NORCHIP.2018.8573468",

language = "English",

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booktitle = "2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) ; Conference date: 30-10-2018 Through 31-10-2018",

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Forsberg, T, Wernehag, J, Sjöland, H & Törmänen, M 2018, A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS. in 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) . IEEE - Institute of Electrical and Electronics Engineers Inc., 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) , Tallin, Estonia, 2018/10/30. https://doi.org/10.1109/NORCHIP.2018.8573468

A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS. / Forsberg, Therese; Wernehag, Johan; Sjöland, Henrik et al.
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) . IEEE - Institute of Electrical and Electronics Engineers Inc., 2018.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

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T1 - A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS

AU - Forsberg, Therese

AU - Wernehag, Johan

AU - Sjöland, Henrik

AU - Törmänen, Markus

PY - 2018/10/30

Y1 - 2018/10/30

N2 - A mm-wave divide-by-two circuit with high injection efficiency, implemented in a 28-nm fully-depleted silicon-on-insulator (FD-SOI) CMOS process is demonstrated stand-alone, as well as using an on-chip voltage controlled oscillator (VCO) as the input signal source. Measurements show that the divider has a 30.1 % tuning range centered at an output frequency of 24 GHz, at an input signal power of -1.5 dBm, and a power consumption of 4.3 mW from a 0.9 V supply. The VCO and divider combination has a tuning range of 10.2 %, centered at an output frequency of 30.2 GHz, at a total power consumption of 6.3 mW, and an output phase noise of -111 dBc/Hz at 10 MHz offset. The active area of the divider is 0.032 mm 2 and of the divider and VCO combination 0.043 mm 2 .

AB - A mm-wave divide-by-two circuit with high injection efficiency, implemented in a 28-nm fully-depleted silicon-on-insulator (FD-SOI) CMOS process is demonstrated stand-alone, as well as using an on-chip voltage controlled oscillator (VCO) as the input signal source. Measurements show that the divider has a 30.1 % tuning range centered at an output frequency of 24 GHz, at an input signal power of -1.5 dBm, and a power consumption of 4.3 mW from a 0.9 V supply. The VCO and divider combination has a tuning range of 10.2 %, centered at an output frequency of 30.2 GHz, at a total power consumption of 6.3 mW, and an output phase noise of -111 dBc/Hz at 10 MHz offset. The active area of the divider is 0.032 mm 2 and of the divider and VCO combination 0.043 mm 2 .

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DO - 10.1109/NORCHIP.2018.8573468

M3 - Paper in conference proceeding

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BT - 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

Y2 - 30 October 2018 through 31 October 2018

ER -

A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS

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