A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS

Siyu Tan, Lars Sundstrom, Mattias Palm, Sven Mattisson, Pietro Andreani

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

Abstract

This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to improve the signal transition speed. The ΔΣ ADC has a simulated SNDR of 73.1 dB for a simulated power consumption of 232mW.

Original languageEnglish
Title of host publication2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019
Subtitle of host publicationNORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings
EditorsJari Nurmi, Peeter Ellervee, Kari Halonen, Juha Roning
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728127699
ISBN (Print)978-1-7281-2770-5
DOIs
Publication statusPublished - 2019 Nov 21
Event5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Helsinki, Finland
Duration: 2019 Oct 292019 Oct 30

Conference

Conference5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019
Country/TerritoryFinland
CityHelsinki
Period2019/10/292019/10/30

Subject classification (UKÄ)

  • Signal Processing

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