A 53.3 Mb/s 4x4 16-QAM MIMO Decoder in 0.35um CMOS

Zhan Guo, Peter Nilsson

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingResearchpeer-review

12 Citations (SciVal)

Abstract

An ASIC implementation of the K-best Schnorr-Euchner decoder is presented for a 4/spl times/4 16-QAM MIMO system. There are several low complexity and low power features incorporated in the proposed VLSI architecture. The chip is fabricated in a 0.35-/spl mu/m CMOS technology. The chip core area is 5.76 mm/sup 2/ with 91 K gates. Furthermore, the decoding throughput that the chip can support is up to 53.3 Mb/s with a core power consumption of 626 mW at 100 MHz clock frequency and 2.8 V supply. The corresponding decoding latency is 2.4 /spl mu/s.
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005.
Pages4947-4950
Volume5
DOIs
Publication statusPublished - 2005
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2005 - Kobe, Japan
Duration: 2005 May 232005 May 26

Publication series

Name
Volume5

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2005
Country/TerritoryJapan
CityKobe
Period2005/05/232005/05/26

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

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