An ASIC implementation of the K-best Schnorr-Euchner decoder is presented for a 4/spl times/4 16-QAM MIMO system. There are several low complexity and low power features incorporated in the proposed VLSI architecture. The chip is fabricated in a 0.35-/spl mu/m CMOS technology. The chip core area is 5.76 mm/sup 2/ with 91 K gates. Furthermore, the decoding throughput that the chip can support is up to 53.3 Mb/s with a core power consumption of 626 mW at 100 MHz clock frequency and 2.8 V supply. The corresponding decoding latency is 2.4 /spl mu/s.
|Conference||IEEE International Symposium on Circuits and Systems (ISCAS), 2005|
|Period||2005/05/23 → 2005/05/26|
- Electrical Engineering, Electronic Engineering, Information Engineering