A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator

Ping Lu, Danfeng Chen, Junyan Ren

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

Abstract

A 5.4GHz multiple-pass ring voltage controlled oscillator (VCO) based phase-locked loop (PLL) is described. For the sake of active devices’ sensitivity to process and temperature regarding ring oscillators, an effective automatic frequency calibration scheme is proposed. A new process-independent differential to single (DTOS) is
used to adjust control voltage range and loop gain. The chip is implemented in 0.18-um CMOS process
and achieves phase noise of -100dBc/Hz@1MHz
and a 40% tuning range.
Original languageEnglish
Title of host publication[Host publication title missing]
Pages39-42
DOIs
Publication statusPublished - 2009
EventIEEE international SOC conference, SOCC 2009 - Belfast, Northern Ireland, Ireland
Duration: 2009 Sep 92009 Sep 11

Conference

ConferenceIEEE international SOC conference, SOCC 2009
Country/TerritoryIreland
Period2009/09/092009/09/11

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

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