Abstract
An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells. An automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The PLL achieves a phase noise of -125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm2 and the current consumption is 30 mA from a 1.2 V supply.
| Original language | English |
|---|---|
| Pages | 65-68 |
| Number of pages | 4 |
| Publication status | Published - 2009 |
| Event | IEEE Asian Solid-State Circuits Conference (ASSCC), 2009 - Taiwan, Taiwan Duration: 2009 Nov 16 → 2009 Nov 18 |
Conference
| Conference | IEEE Asian Solid-State Circuits Conference (ASSCC), 2009 |
|---|---|
| Country/Territory | Taiwan |
| City | Taiwan |
| Period | 2009/11/16 → 2009/11/18 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- RF
- Digitally Controlled Oscillator (DCO)
- Phase Locked Loop (PLL)
- All Digital Phase-Locked Loop (ADPLL)
- Time-to-Digital Converter (TDC)
- CMOS