A 5GHz 90-nm CMOS all digital phase-locked loop

Research output: Contribution to conferencePaper, not in proceedingpeer-review


An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells. An automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The PLL achieves a phase noise of -125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm2 and the current consumption is 30 mA from a 1.2 V supply.
Original languageEnglish
Number of pages4
Publication statusPublished - 2009
EventIEEE Asian Solid-State Circuits Conference (ASSCC), 2009 - Taiwan, Taiwan
Duration: 2009 Nov 162009 Nov 18


ConferenceIEEE Asian Solid-State Circuits Conference (ASSCC), 2009

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

  • RF
  • Digitally Controlled Oscillator (DCO)
  • Phase Locked Loop (PLL)
  • All Digital Phase-Locked Loop (ADPLL)
  • Time-to-Digital Converter (TDC)
  • CMOS


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