A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays

Andreas Axholt, Henrik Sjöland

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review


This paper presents a fully integrated 60 GHz frontend
for phased array receivers. For the first time in the literature
a phase controlled phased locked loop (PC-PLL) is used for
beamforming at 60 GHz. The front-end performs a two stage
frequency down-conversion, first from 60 GHz to 20 GHz, then
from 20 GHz to quadrature baseband. Both the local oscillator
signals at 20 GHz and 40 GHz are generated by a single 20 GHz
QVCO without any frequency multipliers. The measured results
show an input return loss better than -10 dB between 57.5 GHz
and 60.8 GHz, 15 dB voltage gain, and 9 dB noise figure. Twotone
measurements show a -12.5 dBm IIP3, 29 dBm IIP2, and
-24 dBm ICP1dB. The phase control of the PLL has a resolution
of 3.2 degrees and the control range exceeds 360 degrees. The
chip consumes 80 mA from a 1.2 V supply, and measures 1400um
x 660um (900um x 500um excl. pads) incl. LNA, mixers, and
PC-PLL in a 90 nm RF CMOS process.
Original languageEnglish
Title of host publicationAsia-Pacific Microwave Conference 2011
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)978-0-85825-974-4
ISBN (Print)978-1-4577-2034-5
Publication statusPublished - 2011
EventAsia Pacific Microwave Conference - Melbourne, Australia
Duration: 2011 Dec 5 → …


ConferenceAsia Pacific Microwave Conference
Period2011/12/05 → …

Subject classification (UKÄ)

  • Other Electrical Engineering, Electronic Engineering, Information Engineering


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