A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V-T Designs

Christoph Müller, Steffen Malkowsky, Oskar Andersson, Babak Mohammadi, Jens Sparso, Joachim Rodrigues

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

Abstract

This paper proposes a process independent post layout de-synchronization flow implemented in tool command language working on designs operating in the sub-V-T regime. The overhead due to the self-timed operation is combated by introducing full-custom delay elements and latches for a standard 65-nm CMOS process. The flow offers the possibility to adjust granularity based on user requirements. Case studies with different reference designs manifested an average reduction of area and power overhead from 105% to 9% and 174% to 58% in comparison to a full standard cell de-synchronization approach.
Original languageEnglish
Title of host publication2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages380-385
DOIs
Publication statusPublished - 2013
EventIFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) - Istanbul, TURKEY
Duration: 2013 Oct 72013 Oct 9

Conference

ConferenceIFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
Period2013/10/072013/10/09

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

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