A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter

Babak Mohammadi; Joachim Rodrigues

A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A conventional level-shifter is modified to extend the operation range down to subthreshold regime. Leakage current is reduced by utilizing transistor stacking, channel stretching, and reverse body biasing. The design has a standard-cell compliant layout and is fully integrated in a conventional digital design flow. The level-shifter is manufactured in 65 nm CMOS, and functionality is verified by measurements. The proposed design is capable of converting 0.12 to 1.2 V in a single stage, and has a static power consumption of 640 pW at a 0.12 to 1 V conversion. The minimum energy/cycle of 28 fJ/cycle with a conversion speed of 72 MHz was observed at 0.3 to 1 V conversion.

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	990-993
Publication status	Published - 2014
Event	IEEE International Symposium on Circuits and Systems (ISCAS), 2014 - Melbourne, Austrailia, Melbourne, Australia Duration: 2014 Jun 1 → 2014 Jun 5

Publication series

Name
ISSN (Print)	2158-1525
ISSN (Electronic)	0271-4310

Conference

Conference	IEEE International Symposium on Circuits and Systems (ISCAS), 2014
Country/Territory	Australia
City	Melbourne
Period	2014/06/01 → 2014/06/05

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

level-converter
level-shifter
ULV
ultra low power
ultra low voltage
single stage

1 Doctoral Thesis (compilation)

Ultra-low Power Design Approaches in Memories and Assist Techniques
Mohammadi, B., 2017, Department of Electrical and Information Technology, Lund University. 186 p.
Research output: Thesis › Doctoral Thesis (compilation)

Cite this

@inproceedings{46847acbc2c240ed9a8f851eed9dc97d,

title = "A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter",

abstract = "A conventional level-shifter is modified to extend the operation range down to subthreshold regime. Leakage current is reduced by utilizing transistor stacking, channel stretching, and reverse body biasing. The design has a standard-cell compliant layout and is fully integrated in a conventional digital design flow. The level-shifter is manufactured in 65 nm CMOS, and functionality is verified by measurements. The proposed design is capable of converting 0.12 to 1.2 V in a single stage, and has a static power consumption of 640 pW at a 0.12 to 1 V conversion. The minimum energy/cycle of 28 fJ/cycle with a conversion speed of 72 MHz was observed at 0.3 to 1 V conversion.",

keywords = "level-converter, level-shifter, ULV, ultra low power, ultra low voltage, single stage",

author = "Babak Mohammadi and Joachim Rodrigues",

year = "2014",

language = "English",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

pages = "990--993",

booktitle = "2014 IEEE International Symposium on Circuits and Systems (ISCAS)",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems (ISCAS), 2014 ; Conference date: 01-06-2014 Through 05-06-2014",

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TY - GEN

T1 - A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter

AU - Mohammadi, Babak

AU - Rodrigues, Joachim

PY - 2014

Y1 - 2014

N2 - A conventional level-shifter is modified to extend the operation range down to subthreshold regime. Leakage current is reduced by utilizing transistor stacking, channel stretching, and reverse body biasing. The design has a standard-cell compliant layout and is fully integrated in a conventional digital design flow. The level-shifter is manufactured in 65 nm CMOS, and functionality is verified by measurements. The proposed design is capable of converting 0.12 to 1.2 V in a single stage, and has a static power consumption of 640 pW at a 0.12 to 1 V conversion. The minimum energy/cycle of 28 fJ/cycle with a conversion speed of 72 MHz was observed at 0.3 to 1 V conversion.

AB - A conventional level-shifter is modified to extend the operation range down to subthreshold regime. Leakage current is reduced by utilizing transistor stacking, channel stretching, and reverse body biasing. The design has a standard-cell compliant layout and is fully integrated in a conventional digital design flow. The level-shifter is manufactured in 65 nm CMOS, and functionality is verified by measurements. The proposed design is capable of converting 0.12 to 1.2 V in a single stage, and has a static power consumption of 640 pW at a 0.12 to 1 V conversion. The minimum energy/cycle of 28 fJ/cycle with a conversion speed of 72 MHz was observed at 0.3 to 1 V conversion.

KW - level-converter

KW - level-shifter

KW - ULV

KW - ultra low power

KW - ultra low voltage

KW - single stage

M3 - Paper in conference proceeding

SP - 990

EP - 993

BT - 2014 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Circuits and Systems (ISCAS), 2014

Y2 - 1 June 2014 through 5 June 2014

ER -

A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter

Abstract

Publication series

Conference

Subject classification (UKÄ)

Free keywords

Fingerprint

Research output

Ultra-low Power Design Approaches in Memories and Assist Techniques

Cite this