A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter

Babak Mohammadi, Joachim Rodrigues

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review


A conventional level-shifter is modified to extend the operation range down to subthreshold regime. Leakage current is reduced by utilizing transistor stacking, channel stretching, and reverse body biasing. The design has a standard-cell compliant layout and is fully integrated in a conventional digital design flow. The level-shifter is manufactured in 65 nm CMOS, and functionality is verified by measurements. The proposed design is capable of converting 0.12 to 1.2 V in a single stage, and has a static power consumption of 640 pW at a 0.12 to 1 V conversion. The minimum energy/cycle of 28 fJ/cycle with a conversion speed of 72 MHz was observed at 0.3 to 1 V conversion.
Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems (ISCAS)
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Publication statusPublished - 2014
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2014 - Melbourne, Austrailia, Melbourne, Australia
Duration: 2014 Jun 12014 Jun 5

Publication series

ISSN (Print)2158-1525
ISSN (Electronic)0271-4310


ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2014

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

  • level-converter
  • level-shifter
  • ULV
  • ultra low power
  • ultra low voltage
  • single stage


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