A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise

Ahmed Mahmoud; Piero Andreani; Ping Lu

doi:10.1109/NORCHIP.2015.7364356

A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise

Ahmed Mahmoud, Piero Andreani, Ping Lu

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A digital phase-locked loop (DPLL) which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) is presented. The shaped Vernier quantization of TDC greatly improves the in-band phase noise. Also the 2-dimension structure makes DPLL be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO), the DPLL achieves -110dBc/Hz and -130dBc/Hz for in-band and 1MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz. The digital PLL is simulated in a 65nm CMOS process, consuming 11.2mW from a 1.0V supply.

Original language	English
Title of host publication	Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
DOIs	https://doi.org/10.1109/NORCHIP.2015.7364356
Publication status	Published - 2015
Event	Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) - Oslo, Norway Duration: 2015 Oct 26 → 2015 Oct 28

Conference

Conference	Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
Country/Territory	Norway
City	Oslo
Period	2015/10/26 → 2015/10/28

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

Vernier
gated
noise shaping
2-dimension
DPLL
TDC
class-D

Access to Document

10.1109/NORCHIP.2015.7364356

Cite this

@inproceedings{df7ec96634fe42eebacebb463003d4ed,

title = "A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise",

abstract = "A digital phase-locked loop (DPLL) which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) is presented. The shaped Vernier quantization of TDC greatly improves the in-band phase noise. Also the 2-dimension structure makes DPLL be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO), the DPLL achieves -110dBc/Hz and -130dBc/Hz for in-band and 1MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz. The digital PLL is simulated in a 65nm CMOS process, consuming 11.2mW from a 1.0V supply.",

keywords = " Vernier , gated , noise shaping, 2-dimension, DPLL, TDC, class-D",

author = "Ahmed Mahmoud and Piero Andreani and Ping Lu",

year = "2015",

doi = "10.1109/NORCHIP.2015.7364356",

language = "English",

isbn = "978-1-4673-6576-5 ",

booktitle = "Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)",

note = "Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) ; Conference date: 26-10-2015 Through 28-10-2015",

}

Mahmoud, A, Andreani, P & Lu, P 2015, A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise. in Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC). Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), Oslo, Norway, 2015/10/26. https://doi.org/10.1109/NORCHIP.2015.7364356

TY - GEN

T1 - A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise

AU - Mahmoud, Ahmed

AU - Andreani, Piero

AU - Lu, Ping

PY - 2015

Y1 - 2015

N2 - A digital phase-locked loop (DPLL) which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) is presented. The shaped Vernier quantization of TDC greatly improves the in-band phase noise. Also the 2-dimension structure makes DPLL be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO), the DPLL achieves -110dBc/Hz and -130dBc/Hz for in-band and 1MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz. The digital PLL is simulated in a 65nm CMOS process, consuming 11.2mW from a 1.0V supply.

AB - A digital phase-locked loop (DPLL) which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) is presented. The shaped Vernier quantization of TDC greatly improves the in-band phase noise. Also the 2-dimension structure makes DPLL be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO), the DPLL achieves -110dBc/Hz and -130dBc/Hz for in-band and 1MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz. The digital PLL is simulated in a 65nm CMOS process, consuming 11.2mW from a 1.0V supply.

KW - Vernier

KW - gated

KW - noise shaping

KW - 2-dimension

KW - DPLL

KW - TDC

KW - class-D

U2 - 10.1109/NORCHIP.2015.7364356

DO - 10.1109/NORCHIP.2015.7364356

M3 - Paper in conference proceeding

SN - 978-1-4673-6576-5

BT - Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)

T2 - Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)

Y2 - 26 October 2015 through 28 October 2015

ER -

A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise

Abstract

Conference

Subject classification (UKÄ)

Free keywords

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Cite this