A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio

Ji Wang; Manuel Bejarano Carmona; Helgi Hall; Dejan Radjen; Ping Lu

doi:10.1109/NORCHIP.2014.7004720

A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio

Ji Wang, Manuel Bejarano Carmona, Helgi Hall, Dejan Radjen, Ping Lu

Department of Electrical and Information Technology

Lund University

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power radio applications using 130 nm CMOS is presented. The ADC achieves a power consumption of 7/μW according to simulation results. This ultra low power is realized by employing a maximally simplified ADC architecture that consists of a dynamic latch comparator, a charge redistribution digital-to-analog converter (DAC), and a SAR logic block based on transmission gate flip-flops. Working at a supply voltage of 0.8 V, the SAR ADC achieves a FOM of 15 fJ/conversion.

Original language	English
Title of host publication	2014 NORCHIP
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	978-1-4799-5442-1
DOIs	https://doi.org/10.1109/NORCHIP.2014.7004720
Publication status	Published - 2015
Event	32nd NORCHIP Conference, 2014 - Tampere, Tampere, Finland Duration: 2014 Oct 27 → 2014 Oct 28

Conference

Conference	32nd NORCHIP Conference, 2014
Country/Territory	Finland
City	Tampere
Period	2014/10/27 → 2014/10/28

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/NORCHIP.2014.7004720

Cite this

@inproceedings{40fad83ce9e04af8a1f8f873789e16cf,

title = "A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio",

abstract = "A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power radio applications using 130 nm CMOS is presented. The ADC achieves a power consumption of 7/μW according to simulation results. This ultra low power is realized by employing a maximally simplified ADC architecture that consists of a dynamic latch comparator, a charge redistribution digital-to-analog converter (DAC), and a SAR logic block based on transmission gate flip-flops. Working at a supply voltage of 0.8 V, the SAR ADC achieves a FOM of 15 fJ/conversion.",

author = "Ji Wang and Carmona, {Manuel Bejarano} and Helgi Hall and Dejan Radjen and Ping Lu",

year = "2015",

doi = "10.1109/NORCHIP.2014.7004720",

language = "English",

booktitle = "2014 NORCHIP",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "32nd NORCHIP Conference, 2014 ; Conference date: 27-10-2014 Through 28-10-2014",

}

TY - GEN

T1 - A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio

AU - Wang, Ji

AU - Carmona, Manuel Bejarano

AU - Hall, Helgi

AU - Radjen, Dejan

AU - Lu, Ping

PY - 2015

Y1 - 2015

N2 - A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power radio applications using 130 nm CMOS is presented. The ADC achieves a power consumption of 7/μW according to simulation results. This ultra low power is realized by employing a maximally simplified ADC architecture that consists of a dynamic latch comparator, a charge redistribution digital-to-analog converter (DAC), and a SAR logic block based on transmission gate flip-flops. Working at a supply voltage of 0.8 V, the SAR ADC achieves a FOM of 15 fJ/conversion.

AB - A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power radio applications using 130 nm CMOS is presented. The ADC achieves a power consumption of 7/μW according to simulation results. This ultra low power is realized by employing a maximally simplified ADC architecture that consists of a dynamic latch comparator, a charge redistribution digital-to-analog converter (DAC), and a SAR logic block based on transmission gate flip-flops. Working at a supply voltage of 0.8 V, the SAR ADC achieves a FOM of 15 fJ/conversion.

U2 - 10.1109/NORCHIP.2014.7004720

DO - 10.1109/NORCHIP.2014.7004720

M3 - Paper in conference proceeding

BT - 2014 NORCHIP

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 32nd NORCHIP Conference, 2014

Y2 - 27 October 2014 through 28 October 2014

ER -

A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio

Abstract

Conference

Subject classification (UKÄ)

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Cite this