A complete MP3 decoder on a chip

Hugo Hedberg; Thomas Lenart; Henrik Svensson

doi:10.1109/MSE.2005.6

A complete MP3 decoder on a chip

Hugo Hedberg, Thomas Lenart, Henrik Svensson

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

The paper presents the results from a course project which focused on all levels in ASIC design flow by implementing a complete MP3 decoder. Two student teams developed a decoder targeting ASIC and FPGA, respectively. The ASIC decoder, fabricated in a 0.35 μm process from AMI Semiconductor, consumes 40 mW with a supply voltage of 2 V running at 12 MHz. The FPGA decoder has been implemented and verified on a Virtex-II platform

Original language	English
Title of host publication	Proceedings. 2005 IEEE International Conference on Microelectronic Systems Education
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	103-104
ISBN (Print)	0-7695-2374-9
DOIs	https://doi.org/10.1109/MSE.2005.6
Publication status	Published - 2005
Event	Proceedings. 2005 IEEE International Conference on Microelectronic Systems Education (MSE '05) - Anaheim, CA, United States Duration: 2005 Jun 12 → 2005 Jun 14

Conference

Conference	Proceedings. 2005 IEEE International Conference on Microelectronic Systems Education (MSE '05)
Country/Territory	United States
City	Anaheim, CA
Period	2005/06/12 → 2005/06/14

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

MP3 decoder
ASIC design flow
FPGA decoder
0.35 micron
12 MHz
2 V
40 mW
course project

Access to Document

10.1109/MSE.2005.6

Cite this

@inproceedings{b42b51b849d549f9b333d70d04a39696,

title = "A complete MP3 decoder on a chip",

abstract = "The paper presents the results from a course project which focused on all levels in ASIC design flow by implementing a complete MP3 decoder. Two student teams developed a decoder targeting ASIC and FPGA, respectively. The ASIC decoder, fabricated in a 0.35 μm process from AMI Semiconductor, consumes 40 mW with a supply voltage of 2 V running at 12 MHz. The FPGA decoder has been implemented and verified on a Virtex-II platform",

keywords = "MP3 decoder, ASIC design flow, FPGA decoder, 0.35 micron, 12 MHz, 2 V, 40 mW, course project",

author = "Hugo Hedberg and Thomas Lenart and Henrik Svensson",

year = "2005",

doi = "10.1109/MSE.2005.6",

language = "English",

isbn = "0-7695-2374-9",

pages = "103--104",

booktitle = "Proceedings. 2005 IEEE International Conference on Microelectronic Systems Education",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "Proceedings. 2005 IEEE International Conference on Microelectronic Systems Education (MSE '05) ; Conference date: 12-06-2005 Through 14-06-2005",

}

Hedberg, H, Lenart, T & Svensson, H 2005, A complete MP3 decoder on a chip. in Proceedings. 2005 IEEE International Conference on Microelectronic Systems Education. IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 103-104, Proceedings. 2005 IEEE International Conference on Microelectronic Systems Education (MSE '05), Anaheim, CA, United States, 2005/06/12. https://doi.org/10.1109/MSE.2005.6

TY - GEN

T1 - A complete MP3 decoder on a chip

AU - Hedberg, Hugo

AU - Lenart, Thomas

AU - Svensson, Henrik

PY - 2005

Y1 - 2005

N2 - The paper presents the results from a course project which focused on all levels in ASIC design flow by implementing a complete MP3 decoder. Two student teams developed a decoder targeting ASIC and FPGA, respectively. The ASIC decoder, fabricated in a 0.35 μm process from AMI Semiconductor, consumes 40 mW with a supply voltage of 2 V running at 12 MHz. The FPGA decoder has been implemented and verified on a Virtex-II platform

AB - The paper presents the results from a course project which focused on all levels in ASIC design flow by implementing a complete MP3 decoder. Two student teams developed a decoder targeting ASIC and FPGA, respectively. The ASIC decoder, fabricated in a 0.35 μm process from AMI Semiconductor, consumes 40 mW with a supply voltage of 2 V running at 12 MHz. The FPGA decoder has been implemented and verified on a Virtex-II platform

KW - MP3 decoder

KW - ASIC design flow

KW - FPGA decoder

KW - 0.35 micron

KW - 12 MHz

KW - 2 V

KW - 40 mW

KW - course project

U2 - 10.1109/MSE.2005.6

DO - 10.1109/MSE.2005.6

M3 - Paper in conference proceeding

SN - 0-7695-2374-9

SP - 103

EP - 104

BT - Proceedings. 2005 IEEE International Conference on Microelectronic Systems Education

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - Proceedings. 2005 IEEE International Conference on Microelectronic Systems Education (MSE '05)

Y2 - 12 June 2005 through 14 June 2005

ER -

A complete MP3 decoder on a chip

Abstract

Conference

Subject classification (UKÄ)

Free keywords

Access to Document

Fingerprint

Cite this