Research output per year
Research output per year
Siyu Tan, Yun Miao, Mattias Palm, Joachim Neves Rodrigues, Pietro Andreani
Research output: Contribution to journal › Article › peer-review
This work presents a digital calibration technique in continuous-time (CT) delta-sigma (Δ Σ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT Δ Σ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.
Original language | English |
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Pages (from-to) | 273-282 |
Number of pages | 10 |
Journal | Analog Integrated Circuits and Signal Processing |
Volume | 89 |
Issue number | 2 |
DOIs | |
Publication status | Published - 2016 Nov 1 |
Research output: Thesis › Doctoral Thesis (compilation)