A continuous-time delta-sigma ADC with integrated digital background calibration

Siyu Tan; Yun Miao; Mattias Palm; Joachim Neves Rodrigues; Pietro Andreani

doi:10.1007/s10470-016-0800-7

A continuous-time delta-sigma ADC with integrated digital background calibration

Siyu Tan, Yun Miao, Mattias Palm, Joachim Neves Rodrigues, Pietro Andreani

Research output: Contribution to journal › Article › peer-review

Abstract

This work presents a digital calibration technique in continuous-time (CT) delta-sigma (Δ Σ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT Δ Σ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

Original language	English
Pages (from-to)	273-282
Number of pages	10
Journal	Analog Integrated Circuits and Signal Processing
Volume	89
Issue number	2
DOIs	https://doi.org/10.1007/s10470-016-0800-7
Publication status	Published - 2016 Nov 1

Subject classification (UKÄ)

Signal Processing

Free keywords

Background calibration
Continuous-time
Delta-sigma modulator
Digital calibration

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10.1007/s10470-016-0800-7

Cite this

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title = "A continuous-time delta-sigma ADC with integrated digital background calibration",

abstract = "This work presents a digital calibration technique in continuous-time (CT) delta-sigma (Δ Σ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT Δ Σ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.",

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author = "Siyu Tan and Yun Miao and Mattias Palm and Rodrigues, \{Joachim Neves\} and Pietro Andreani",

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T1 - A continuous-time delta-sigma ADC with integrated digital background calibration

AU - Tan, Siyu

AU - Miao, Yun

AU - Palm, Mattias

AU - Rodrigues, Joachim Neves

AU - Andreani, Pietro

PY - 2016/11/1

Y1 - 2016/11/1

N2 - This work presents a digital calibration technique in continuous-time (CT) delta-sigma (Δ Σ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT Δ Σ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

AB - This work presents a digital calibration technique in continuous-time (CT) delta-sigma (Δ Σ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT Δ Σ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

KW - Background calibration

KW - Continuous-time

KW - Delta-sigma modulator

KW - Digital calibration

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JO - Analog Integrated Circuits and Signal Processing

JF - Analog Integrated Circuits and Signal Processing

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ER -

A continuous-time delta-sigma ADC with integrated digital background calibration

Abstract

Subject classification (UKÄ)

Free keywords

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