A Digital Baseband for Low Power FSK Based Receiver in 65 nm CMOS

Syed Muhammad Yasser Sherazi, Henrik Sjöland, Peter Nilsson

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

Abstract

The design of a digital baseband for a low power wireless receiver in 65 nm CMOS is presented. It consists of decimation filtering, matched filters for data detection, and preamble based synchronization. The circuit was designed using low threshold devices in both low power (LP-LVT) and general-purpose (GP-LVT) domains. The fabricated circuits were functionally verified, and silicon measurements show a minimum energy dissipation of around 454 pJ and 708 pJ per output bit at a rate of 500 kbit/s for the LP-LVT and GP-LVT implementations, respectively.
Original languageEnglish
Title of host publication[Host publication title missing]
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Number of pages4
Publication statusPublished - 2014
EventIEEE 21th International Conference on Electronics, Circuits and Systems, 2014 - Marseille, France
Duration: 2014 Dec 72014 Dec 10

Conference

ConferenceIEEE 21th International Conference on Electronics, Circuits and Systems, 2014
Abbreviated titleICECS 2014
Country/TerritoryFrance
CityMarseille
Period2014/12/072014/12/10

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

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