Abstract
The design of a digital baseband for a low power wireless receiver in 65 nm CMOS is presented. It consists of decimation filtering, matched filters for data detection, and preamble based synchronization. The circuit was designed using low threshold devices in both low power (LP-LVT) and general-purpose (GP-LVT) domains. The fabricated circuits were functionally verified, and silicon measurements show a minimum energy dissipation of around 454 pJ and 708 pJ per output bit at a rate of 500 kbit/s for the LP-LVT and GP-LVT implementations, respectively.
Original language | English |
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Title of host publication | [Host publication title missing] |
Publisher | IEEE - Institute of Electrical and Electronics Engineers Inc. |
Number of pages | 4 |
Publication status | Published - 2014 |
Event | IEEE 21th International Conference on Electronics, Circuits and Systems, 2014 - Marseille, France Duration: 2014 Dec 7 → 2014 Dec 10 |
Conference
Conference | IEEE 21th International Conference on Electronics, Circuits and Systems, 2014 |
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Abbreviated title | ICECS 2014 |
Country/Territory | France |
City | Marseille |
Period | 2014/12/07 → 2014/12/10 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering