A Digital PLL with a Multi-Delay Coarse-Fine TDC

Ying Wu, Ping Lu, Pietro Andreani

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review


A 5GHz digital frequency synthesizer achieving a low noise for wireless RF application is presented. This architecture uses a multi-delay coarse-fine Time-to-Digital Converter (TDC) to achieve both the large detection range and fine resolution. A Digitally Controlled Oscillator (DCO) based on capacitive degeneration in LC-Tank is also implement-ed. The DCO achieves frequency quantization step of 300 Hz without any dithering. Simulated phase noise at 5 GHz carrier frequency is -125 and -151 dBc/Hz at 1 MHz and 20 MHz offset, respectively. The Digital phase-locked loop (DPLL) is realized in 90nm CMOS process and consumes 14mA from a 1.2V supply.
Original languageEnglish
Title of host publication[Host publication title missing]
Number of pages4
Publication statusPublished - 2011
Event29th Norchip conference, 2011 - Lund, Lund, Sweden
Duration: 2011 Nov 142011 Nov 15


Conference29th Norchip conference, 2011

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering


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