TY - GEN
T1 - A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs
AU - Olsson, Thomas
AU - Nilsson, Peter
AU - Meincke, Thomas
AU - Hemani, Ahmed
AU - Torkelson, Mats
PY - 2000
Y1 - 2000
N2 - Partitioning large high-speed globally synchronous ASICs into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces the power consumption. However, to achieve these positive effects, the blocks need on-chip clock generators having properties such as small area and low power consumption. Therefore, a low power, high frequency, small area digitally controlled on-chip clock generator is designed and fabricated using a 0.35 μm process. The clock generator delivers up to 1.15 GHz at 3.3 V supply voltage. At 1 V supply voltage, it delivers up to 92 MHz while consuming 0.16 mW
AB - Partitioning large high-speed globally synchronous ASICs into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces the power consumption. However, to achieve these positive effects, the blocks need on-chip clock generators having properties such as small area and low power consumption. Therefore, a low power, high frequency, small area digitally controlled on-chip clock generator is designed and fabricated using a 0.35 μm process. The clock generator delivers up to 1.15 GHz at 3.3 V supply voltage. At 1 V supply voltage, it delivers up to 92 MHz while consuming 0.16 mW
KW - low-power electronics
KW - application specific integrated circuits
KW - clocks
KW - pulse generators
KW - multiplying circuits
M3 - Paper in conference proceeding
SN - 0-7803-5482-6
VL - 3
SP - 13
EP - 16
BT - The 2000 IEEE International Symposium on Circuits and Systems. Proceedings.
T2 - IEEE International Symposium on Circuits and Systems (ISCAS), 2000
Y2 - 28 May 2000 through 31 May 2000
ER -