A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs

Thomas Olsson, Peter Nilsson, Thomas Meincke, Ahmed Hemani, Mats Torkelson

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingResearchpeer-review

15 Citations (Scopus)

Abstract

Partitioning large high-speed globally synchronous ASICs into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces the power consumption. However, to achieve these positive effects, the blocks need on-chip clock generators having properties such as small area and low power consumption. Therefore, a low power, high frequency, small area digitally controlled on-chip clock generator is designed and fabricated using a 0.35 μm process. The clock generator delivers up to 1.15 GHz at 3.3 V supply voltage. At 1 V supply voltage, it delivers up to 92 MHz while consuming 0.16 mW
Original languageEnglish
Title of host publicationThe 2000 IEEE International Symposium on Circuits and Systems. Proceedings.
Pages13-16
Volume3
Publication statusPublished - 2000
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2000 - Geneva, Switzerland
Duration: 2000 May 282000 May 31

Publication series

Name
Volume3

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2000
Country/TerritorySwitzerland
CityGeneva
Period2000/05/282000/05/31

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • low-power electronics
  • application specific integrated circuits
  • clocks
  • pulse generators
  • multiplying circuits

Fingerprint

Dive into the research topics of 'A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs'. Together they form a unique fingerprint.

Cite this