@inproceedings{84479eb23edd4fbbae7bc23f477ea889,
title = "A digitally controlled PLL for digital SOCs",
abstract = "A fully integrated digitally controlled PLL used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm2. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system simulation and change of process. A new time-to-digital converter with simulated resolution of 250 ps is made for the next PLL.",
keywords = "Digital systems",
author = "Thomas Olsson and Peter Nilsson",
year = "2003",
doi = "10.1109/ISCAS.2003.1206308",
language = "English",
volume = "5",
publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",
pages = "437--440",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",
address = "United States",
note = "Proceedings of the 2003 IEEE International Symposium on Circuits and Systems ; Conference date: 25-05-2003 Through 28-05-2003",
}