A Floating-Point 16 × 16 SVD Accelerator for Beyond-5G Large Intelligent Surfaces

Mohammad Attari; Jesus Rodriguez Sanchez; Liang Liu

doi:10.1109/MWSCAS57524.2023.10406077

A Floating-Point 16 × 16 SVD Accelerator for Beyond-5G Large Intelligent Surfaces

Mohammad Attari, Jesus Rodriguez Sanchez, Liang Liu

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

Beyond-5G wireless communication systems will feature advanced, key technologies such as large intelligent surfaces (LISs) composed of a very large number of antenna elements. The concomitant tremendous data rate requirements, due to the communication between these antennas, necessitate careful algorithm-architecture codesign. This paper presents an application-specific integrated circuit (ASIC) accelerator designed for efficient computation of singular value decomposition (SVD) utilized in distributed and scalable massive multiple-input multiple-output (MIMO) systems equipped with LISs. The design supports SVD calculation for 8 × 8 and 16 × 16 matrices and is synthesized using the GF -22nm fully depleted silicon-on-insulator (FD-SOI) technology with a clock frequency approaching 580 MHz. It takes up an area of 0.33 mm2 and consumes 219 mW of power. The system can pump out results at a cadence of 270/90 kSVDs/s, with a mean squared error (MSE) of 10-3, for 8 × 8 and 16 × 16 matrices, respectively.

Original language	English
Title of host publication	2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	967-971
Number of pages	5
ISBN (Electronic)	9798350302103
DOIs	https://doi.org/10.1109/MWSCAS57524.2023.10406077
Publication status	Published - 2023
Event	2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023 - Tempe, United States Duration: 2023 Aug 6 → 2023 Aug 9

Conference

Conference	2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
Country/Territory	United States
City	Tempe
Period	2023/08/06 → 2023/08/09

Subject classification (UKÄ)

Other Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

accelerator
floating-point
Golub-Kahan
hardware
Jacobi
large intelligent surface
massive MIMO
Singular value decomposition

Access to Document

10.1109/MWSCAS57524.2023.10406077

1 Doctoral Thesis (compilation)

Application Specific Instruction-set Processors for Massive MIMO Systems
Attari, M., 2024 Oct 11, Lund University. 122 p.
Research output: Thesis › Doctoral Thesis (compilation)

Open Access
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Cite this

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title = "A Floating-Point 16 × 16 SVD Accelerator for Beyond-5G Large Intelligent Surfaces",

abstract = "Beyond-5G wireless communication systems will feature advanced, key technologies such as large intelligent surfaces (LISs) composed of a very large number of antenna elements. The concomitant tremendous data rate requirements, due to the communication between these antennas, necessitate careful algorithm-architecture codesign. This paper presents an application-specific integrated circuit (ASIC) accelerator designed for efficient computation of singular value decomposition (SVD) utilized in distributed and scalable massive multiple-input multiple-output (MIMO) systems equipped with LISs. The design supports SVD calculation for 8 × 8 and 16 × 16 matrices and is synthesized using the GF -22nm fully depleted silicon-on-insulator (FD-SOI) technology with a clock frequency approaching 580 MHz. It takes up an area of 0.33 mm2 and consumes 219 mW of power. The system can pump out results at a cadence of 270/90 kSVDs/s, with a mean squared error (MSE) of 10-3, for 8 × 8 and 16 × 16 matrices, respectively.",

keywords = "accelerator, floating-point, Golub-Kahan, hardware, Jacobi, large intelligent surface, massive MIMO, Singular value decomposition",

author = "Mohammad Attari and Sanchez, {Jesus Rodriguez} and Liang Liu",

year = "2023",

doi = "10.1109/MWSCAS57524.2023.10406077",

language = "English",

pages = "967--971",

booktitle = "2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023 ; Conference date: 06-08-2023 Through 09-08-2023",

}

Attari, M, Sanchez, JR & Liu, L 2023, A Floating-Point 16 × 16 SVD Accelerator for Beyond-5G Large Intelligent Surfaces. in 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023. IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 967-971, 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023, Tempe, United States, 2023/08/06. https://doi.org/10.1109/MWSCAS57524.2023.10406077

A Floating-Point 16 × 16 SVD Accelerator for Beyond-5G Large Intelligent Surfaces. / Attari, Mohammad; Sanchez, Jesus Rodriguez; Liu, Liang.
2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023. IEEE - Institute of Electrical and Electronics Engineers Inc., 2023. p. 967-971.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - A Floating-Point 16 × 16 SVD Accelerator for Beyond-5G Large Intelligent Surfaces

AU - Attari, Mohammad

AU - Sanchez, Jesus Rodriguez

AU - Liu, Liang

PY - 2023

Y1 - 2023

N2 - Beyond-5G wireless communication systems will feature advanced, key technologies such as large intelligent surfaces (LISs) composed of a very large number of antenna elements. The concomitant tremendous data rate requirements, due to the communication between these antennas, necessitate careful algorithm-architecture codesign. This paper presents an application-specific integrated circuit (ASIC) accelerator designed for efficient computation of singular value decomposition (SVD) utilized in distributed and scalable massive multiple-input multiple-output (MIMO) systems equipped with LISs. The design supports SVD calculation for 8 × 8 and 16 × 16 matrices and is synthesized using the GF -22nm fully depleted silicon-on-insulator (FD-SOI) technology with a clock frequency approaching 580 MHz. It takes up an area of 0.33 mm2 and consumes 219 mW of power. The system can pump out results at a cadence of 270/90 kSVDs/s, with a mean squared error (MSE) of 10-3, for 8 × 8 and 16 × 16 matrices, respectively.

AB - Beyond-5G wireless communication systems will feature advanced, key technologies such as large intelligent surfaces (LISs) composed of a very large number of antenna elements. The concomitant tremendous data rate requirements, due to the communication between these antennas, necessitate careful algorithm-architecture codesign. This paper presents an application-specific integrated circuit (ASIC) accelerator designed for efficient computation of singular value decomposition (SVD) utilized in distributed and scalable massive multiple-input multiple-output (MIMO) systems equipped with LISs. The design supports SVD calculation for 8 × 8 and 16 × 16 matrices and is synthesized using the GF -22nm fully depleted silicon-on-insulator (FD-SOI) technology with a clock frequency approaching 580 MHz. It takes up an area of 0.33 mm2 and consumes 219 mW of power. The system can pump out results at a cadence of 270/90 kSVDs/s, with a mean squared error (MSE) of 10-3, for 8 × 8 and 16 × 16 matrices, respectively.

KW - accelerator

KW - floating-point

KW - Golub-Kahan

KW - hardware

KW - Jacobi

KW - large intelligent surface

KW - massive MIMO

KW - Singular value decomposition

U2 - 10.1109/MWSCAS57524.2023.10406077

DO - 10.1109/MWSCAS57524.2023.10406077

M3 - Paper in conference proceeding

AN - SCOPUS:85185376092

SP - 967

EP - 971

BT - 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023

Y2 - 6 August 2023 through 9 August 2023

ER -

A Floating-Point 16 × 16 SVD Accelerator for Beyond-5G Large Intelligent Surfaces

Abstract

Conference

Subject classification (UKÄ)

Free keywords

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Research output

Application Specific Instruction-set Processors for Massive MIMO Systems

Cite this