A fully Integrated Standard-Cell Digital PLL

Thomas Olsson; Peter Nilsson

doi:10.1049/el:20010160

A fully Integrated Standard-Cell Digital PLL

Thomas Olsson, Peter Nilsson

Research output: Contribution to journal › Article › peer-review

Abstract

A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm2

Original language	English
Pages (from-to)	211-212
Journal	Electronics Letters
Volume	37
Issue number	4
DOIs	https://doi.org/10.1049/el:20010160
Publication status	Published - 2001

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

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10.1049/el:20010160

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title = "A fully Integrated Standard-Cell Digital PLL",

abstract = "A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm2",

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AB - A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm2

UR - https://www.scopus.com/pages/publications/6644224989

U2 - 10.1049/el:20010160

DO - 10.1049/el:20010160

M3 - Article

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JO - Electronics Letters

JF - Electronics Letters

IS - 4

ER -

A fully Integrated Standard-Cell Digital PLL

Abstract

Subject classification (UKÄ)

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