A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS

Ping Lu; Pietro Andreani

doi:10.1109/NORCHIP.2010.5669467

A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves the in-band TDC noise contribution for an ADPLL. Operating at 1.2-V supply with 250MHz clock, the chip achieves a less-than-10ps coarse resolution (varies with digital control bits) and consumes only 3.6-mA.

Original language	English
Title of host publication	[Host publication title missing]
Number of pages	4
DOIs	https://doi.org/10.1109/NORCHIP.2010.5669467
Publication status	Published - 2010
Event	NORCHIP Conference, 2010 - Tampere, Finland Duration: 2010 Nov 15 → 2010 Nov 16

Conference

Conference	NORCHIP Conference, 2010
Country/Territory	Finland
City	Tampere
Period	2010/11/15 → 2010/11/16

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/NORCHIP.2010.5669467

Cite this

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title = "A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS",

abstract = "A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves the in-band TDC noise contribution for an ADPLL. Operating at 1.2-V supply with 250MHz clock, the chip achieves a less-than-10ps coarse resolution (varies with digital control bits) and consumes only 3.6-mA.",

author = "Ping Lu and Pietro Andreani",

year = "2010",

doi = "10.1109/NORCHIP.2010.5669467",

language = "English",

isbn = "978-1-4244-8972-5",

booktitle = "[Host publication title missing]",

note = "NORCHIP Conference, 2010 ; Conference date: 15-11-2010 Through 16-11-2010",

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TY - GEN

T1 - A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS

AU - Lu, Ping

AU - Andreani, Pietro

PY - 2010

Y1 - 2010

N2 - A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves the in-band TDC noise contribution for an ADPLL. Operating at 1.2-V supply with 250MHz clock, the chip achieves a less-than-10ps coarse resolution (varies with digital control bits) and consumes only 3.6-mA.

AB - A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves the in-band TDC noise contribution for an ADPLL. Operating at 1.2-V supply with 250MHz clock, the chip achieves a less-than-10ps coarse resolution (varies with digital control bits) and consumes only 3.6-mA.

U2 - 10.1109/NORCHIP.2010.5669467

DO - 10.1109/NORCHIP.2010.5669467

M3 - Paper in conference proceeding

SN - 978-1-4244-8972-5

BT - [Host publication title missing]

T2 - NORCHIP Conference, 2010

Y2 - 15 November 2010 through 16 November 2010

ER -

A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS

Abstract

Conference

Subject classification (UKÄ)

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