Abstract
Low-complexity VLSI (very large scale integration) architecture of the square root algorithm is proposed for MIMO (multiple-input multiple-output) detection. As a modification to the traditional QR triangular array based architecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade-offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA (field programmable gate arrays). For a 4-transmit and 4-receive antennas MIMO system using QPSK (quarter phase-shift keying) modulation scheme, a detecting throughput of 80 Mb/s can be achieved
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the IASTED International Conference on Circuits, Signals, and Systems |
| Publisher | ACTA Press |
| Pages | 304-309 |
| ISBN (Print) | 0-88986-351-2 |
| Publication status | Published - 2003 |
| Event | IASTED International Conference on Circuits, Signals and Systems, 2003 - Cancun, Mexico Duration: 2003 May 19 → 2003 May 21 |
Conference
| Conference | IASTED International Conference on Circuits, Signals and Systems, 2003 |
|---|---|
| Country/Territory | Mexico |
| City | Cancun |
| Period | 2003/05/19 → 2003/05/21 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- multiple-input multiple-output
- square root algorithm
- power consumption
- finite word length analysis
- VirtexE series Xilinx FPGA
- field programmable gate arrays
- 4-transmit antennas
- quarter phase-shift keying
- 4-receive antennas
- QPSK modulation
- MIMO detection
- VLSI architecture
- very large scale integration