A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet

Ping Lu; Fan Ye; Junyan Ren

doi:10.1109/ISCAS.2006.1693126

A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet

Ping Lu, Fan Ye, Junyan Ren

External Organization - Unknown

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

A frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Base-T mode is described. A dynamic voltage-mode phase interpolator is used and a more precise analysis and calculation on degressive interpolating resistors are given. The design not only meets the transmitter's requirement of very accurate rising (falling) edge control but also offers much finer time-interval clocks compared to VCO natural multi-phase outputs. The chip was implemented in SMIC 0.18-mum standard CMOS technology and achieves an RMS jitter of 11ps with the crystal oscillator reference RMS jitter of 16ps. The power is smaller than 4mW from a 1.8V power supply in all modes

Original language	English
Title of host publication	[Host publication title missing]
Pages	2481-2484
DOIs	https://doi.org/10.1109/ISCAS.2006.1693126
Publication status	Published - 2006
Externally published	Yes
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2006 - Island of Kos, Greece Duration: 2006 May 21 → 2006 May 24

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2006
Country/Territory	Greece
City	Island of Kos
Period	2006/05/21 → 2006/05/24

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/ISCAS.2006.1693126

Cite this

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title = "A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet",

abstract = "A frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Base-T mode is described. A dynamic voltage-mode phase interpolator is used and a more precise analysis and calculation on degressive interpolating resistors are given. The design not only meets the transmitter's requirement of very accurate rising (falling) edge control but also offers much finer time-interval clocks compared to VCO natural multi-phase outputs. The chip was implemented in SMIC 0.18-mum standard CMOS technology and achieves an RMS jitter of 11ps with the crystal oscillator reference RMS jitter of 16ps. The power is smaller than 4mW from a 1.8V power supply in all modes",

author = "Ping Lu and Fan Ye and Junyan Ren",

year = "2006",

doi = "10.1109/ISCAS.2006.1693126",

language = "English",

isbn = "0-7803-9389-9",

pages = "2481--2484",

booktitle = "[Host publication title missing]",

note = "IEEE International Symposium on Circuits and Systems, ISCAS 2006 ; Conference date: 21-05-2006 Through 24-05-2006",

}

TY - GEN

T1 - A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet

AU - Lu, Ping

AU - Ye, Fan

AU - Ren, Junyan

PY - 2006

Y1 - 2006

N2 - A frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Base-T mode is described. A dynamic voltage-mode phase interpolator is used and a more precise analysis and calculation on degressive interpolating resistors are given. The design not only meets the transmitter's requirement of very accurate rising (falling) edge control but also offers much finer time-interval clocks compared to VCO natural multi-phase outputs. The chip was implemented in SMIC 0.18-mum standard CMOS technology and achieves an RMS jitter of 11ps with the crystal oscillator reference RMS jitter of 16ps. The power is smaller than 4mW from a 1.8V power supply in all modes

AB - A frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Base-T mode is described. A dynamic voltage-mode phase interpolator is used and a more precise analysis and calculation on degressive interpolating resistors are given. The design not only meets the transmitter's requirement of very accurate rising (falling) edge control but also offers much finer time-interval clocks compared to VCO natural multi-phase outputs. The chip was implemented in SMIC 0.18-mum standard CMOS technology and achieves an RMS jitter of 11ps with the crystal oscillator reference RMS jitter of 16ps. The power is smaller than 4mW from a 1.8V power supply in all modes

U2 - 10.1109/ISCAS.2006.1693126

DO - 10.1109/ISCAS.2006.1693126

M3 - Paper in conference proceeding

SN - 0-7803-9389-9

SP - 2481

EP - 2484

BT - [Host publication title missing]

T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2006

Y2 - 21 May 2006 through 24 May 2006

ER -

A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet

Abstract

Conference

Subject classification (UKÄ)

Access to Document

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Cite this