Abstract
A complex multiplier has been designed for use in a pipelined fast fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input to output delay as short as possible. A new architecture based on distributed arithmetic and Wallace-trees has been developed and is compared to a previous multiplier realized as a regular distributed arithmetic array. The simulated gain in speed for the presented multiplier is about 100%. For verification, the multiplier is fabricated in a three metal-layer 0.5µ CMOS process using a standard cell library. The fabricated multiplier chip has been functionally verified.
| Original language | English |
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| Pages | 204-207 |
| Publication status | Published - 1998 |
| Event | European Solid-State Circuits Conference (ESSCIRC), 1998 - Hague, Netherlands Duration: 1998 Sept 22 → 1998 Sept 24 Conference number: 24 |
Conference
| Conference | European Solid-State Circuits Conference (ESSCIRC), 1998 |
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| Country/Territory | Netherlands |
| City | Hague |
| Period | 1998/09/22 → 1998/09/24 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering