A low-power 8-bit folding A/D converter with improved accuracy

Cheng Chen; Jiren Yuan

doi:10.1109/ICSICT.2006.306375

A low-power 8-bit folding A/D converter with improved accuracy

Cheng Chen, Jiren Yuan

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

In this paper, an accuracy improving method for calibration of mismatch-induced errors in folding A/D converter is presented. With dynamic auto-zero calibration for the folder, the transistor size of folding differential input pairs can be reduced considerably while keeping integral nonlinearity (INL) low. Using this technique, an 8-bit folding A/D converter is designed and simulated in MATLAB. Because of the calibration, conventional preamplifiers and offset averaging network before the folders are removed, saving a large power consumption and chip area. Results are demonstrated, showing the improved accuracy and the good agreement with the theoretical prediction

Original language	English
Title of host publication	2006 8th International Conference on Solid-State and Integrated Circuit Technology
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Number of pages	4
ISBN (Print)	1-4244-0160-7
DOIs	https://doi.org/10.1109/ICSICT.2006.306375
Publication status	Published - 2006
Event	2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China Duration: 2006 Oct 23 → 2006 Oct 26

Conference

Conference	2006 8th International Conference on Solid-State and Integrated Circuit Technology
Country/Territory	China
City	Shanghai
Period	2006/10/23 → 2006/10/26

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

analog-digital converter
folding A/D converter
folding differential input
dynamic auto-zero calibration
MATLAB
8 bit
integral nonlinearity

Access to Document

10.1109/ICSICT.2006.306375

Cite this

@inproceedings{d1313c0b51e74bbd9dfea21b9563425a,

title = "A low-power 8-bit folding A/D converter with improved accuracy",

abstract = "In this paper, an accuracy improving method for calibration of mismatch-induced errors in folding A/D converter is presented. With dynamic auto-zero calibration for the folder, the transistor size of folding differential input pairs can be reduced considerably while keeping integral nonlinearity (INL) low. Using this technique, an 8-bit folding A/D converter is designed and simulated in MATLAB. Because of the calibration, conventional preamplifiers and offset averaging network before the folders are removed, saving a large power consumption and chip area. Results are demonstrated, showing the improved accuracy and the good agreement with the theoretical prediction",

keywords = "analog-digital converter, folding A/D converter, folding differential input, dynamic auto-zero calibration, MATLAB, 8 bit, integral nonlinearity",

author = "Cheng Chen and Jiren Yuan",

year = "2006",

doi = "10.1109/ICSICT.2006.306375",

language = "English",

isbn = "1-4244-0160-7",

booktitle = "2006 8th International Conference on Solid-State and Integrated Circuit Technology",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "2006 8th International Conference on Solid-State and Integrated Circuit Technology ; Conference date: 23-10-2006 Through 26-10-2006",

}

Chen, C & Yuan, J 2006, A low-power 8-bit folding A/D converter with improved accuracy. in 2006 8th International Conference on Solid-State and Integrated Circuit Technology. IEEE - Institute of Electrical and Electronics Engineers Inc., 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 2006/10/23. https://doi.org/10.1109/ICSICT.2006.306375

TY - GEN

T1 - A low-power 8-bit folding A/D converter with improved accuracy

AU - Chen, Cheng

AU - Yuan, Jiren

PY - 2006

Y1 - 2006

N2 - In this paper, an accuracy improving method for calibration of mismatch-induced errors in folding A/D converter is presented. With dynamic auto-zero calibration for the folder, the transistor size of folding differential input pairs can be reduced considerably while keeping integral nonlinearity (INL) low. Using this technique, an 8-bit folding A/D converter is designed and simulated in MATLAB. Because of the calibration, conventional preamplifiers and offset averaging network before the folders are removed, saving a large power consumption and chip area. Results are demonstrated, showing the improved accuracy and the good agreement with the theoretical prediction

AB - In this paper, an accuracy improving method for calibration of mismatch-induced errors in folding A/D converter is presented. With dynamic auto-zero calibration for the folder, the transistor size of folding differential input pairs can be reduced considerably while keeping integral nonlinearity (INL) low. Using this technique, an 8-bit folding A/D converter is designed and simulated in MATLAB. Because of the calibration, conventional preamplifiers and offset averaging network before the folders are removed, saving a large power consumption and chip area. Results are demonstrated, showing the improved accuracy and the good agreement with the theoretical prediction

KW - analog-digital converter

KW - folding A/D converter

KW - folding differential input

KW - dynamic auto-zero calibration

KW - MATLAB

KW - 8 bit

KW - integral nonlinearity

U2 - 10.1109/ICSICT.2006.306375

DO - 10.1109/ICSICT.2006.306375

M3 - Paper in conference proceeding

SN - 1-4244-0160-7

BT - 2006 8th International Conference on Solid-State and Integrated Circuit Technology

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 2006 8th International Conference on Solid-State and Integrated Circuit Technology

Y2 - 23 October 2006 through 26 October 2006

ER -

A low-power 8-bit folding A/D converter with improved accuracy

Abstract

Conference

Subject classification (UKÄ)

Free keywords

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