A low-power 8-bit folding A/D converter with improved accuracy

Cheng Chen, Jiren Yuan

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

1 Citation (SciVal)

Abstract

In this paper, an accuracy improving method for calibration of mismatch-induced errors in folding A/D converter is presented. With dynamic auto-zero calibration for the folder, the transistor size of folding differential input pairs can be reduced considerably while keeping integral nonlinearity (INL) low. Using this technique, an 8-bit folding A/D converter is designed and simulated in MATLAB. Because of the calibration, conventional preamplifiers and offset averaging network before the folders are removed, saving a large power consumption and chip area. Results are demonstrated, showing the improved accuracy and the good agreement with the theoretical prediction
Original languageEnglish
Title of host publication2006 8th International Conference on Solid-State and Integrated Circuit Technology
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Print)1-4244-0160-7
DOIs
Publication statusPublished - 2006
Event2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
Duration: 2006 Oct 232006 Oct 26

Conference

Conference2006 8th International Conference on Solid-State and Integrated Circuit Technology
Country/TerritoryChina
CityShanghai
Period2006/10/232006/10/26

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • analog-digital converter
  • folding A/D converter
  • folding differential input
  • dynamic auto-zero calibration
  • MATLAB
  • 8 bit
  • integral nonlinearity

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